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60 lines
1.9 KiB
60 lines
1.9 KiB
/* |
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* Copyright (c) 2019 - 2020 Nordic Semiconductor ASA |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#if defined(CONFIG_CPU_CORTEX_M_HAS_VTOR) |
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/* |
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* In an MCU with VTOR, the VTOR.TBLOFF is set to the start address of the |
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* exc_vector_table (i.e. _vector_start) during initialization. Therefore, |
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* exc_vector_table must respect the alignment requirements of VTOR.TBLOFF |
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* described below. |
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*/ |
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) |
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/* VTOR bits 0:7 are reserved (RES0). This requires that the base address |
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* of the vector table is 64-word aligned. |
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*/ |
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. = ALIGN( 1 << LOG2CEIL(4 * 64) ); |
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) |
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/* VTOR bits 0:6 are reserved (RES0). This requires that the base address |
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* of the vector table is 32-word aligned. |
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*/ |
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. = ALIGN( 1 << LOG2CEIL(4 * 32) ); |
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#else |
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#error "Unsupported architecture variant" |
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#endif |
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/* When setting TBLOFF in VTOR we must align the offset to the number of |
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* exception entries in the vector table. The minimum alignment of 32 words |
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* is sufficient for the 16 ARM Core exceptions and up to 16 HW interrupts. |
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* For more than 16 HW interrupts, we adjust the alignment by rounding up |
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* to the next power of two; this restriction guarantees a functional VTOR |
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* setting in any Cortex-M implementation (might not be required in every |
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* Cortex-M processor). |
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*/ |
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. = ALIGN( 1 << LOG2CEIL(4 * (16 + CONFIG_NUM_IRQS)) ); |
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#endif |
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#ifdef CONFIG_ARM_ZIMAGE_HEADER |
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/* |
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* For AArch32 (A/R), VBAR has Bits [4:0] = RES0. |
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* For AArch32 (M), VTOR has Bits [6:0] = RES0. Thus, vector start address |
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* should be aligned in such a way so that it satisfies the requirements of |
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* VBAR and VTOR ie Bits [6:0] = 0. |
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*/ |
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. = ALIGN( 0x80 ); |
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#endif |
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_vector_start = .; |
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KEEP(*(.exc_vector_table)) |
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KEEP(*(".exc_vector_table.*")) |
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#if LINKER_ZEPHYR_FINAL && defined(CONFIG_ISR_TABLES_LOCAL_DECLARATION) |
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INCLUDE isr_tables_vt.ld |
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#else |
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KEEP(*(.vectors)) |
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#endif |
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_vector_end = .;
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