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632 lines
13 KiB
632 lines
13 KiB
/* |
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* Copyright 2022-2023, NXP |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <mem.h> |
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#include <arm/armv8-m.dtsi> |
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#include <zephyr/dt-bindings/adc/adc.h> |
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#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h> |
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#include <zephyr/dt-bindings/gpio/gpio.h> |
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#include <zephyr/dt-bindings/i2c/i2c.h> |
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#include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h> |
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#include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h> |
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> |
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/ { |
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chosen { |
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zephyr,entropy = &trng; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu0: cpu@0 { |
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compatible = "arm,cortex-m33f"; |
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reg = <0>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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cpu-power-states = <&idle &suspend>; |
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mpu: mpu@e000ed90 { |
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compatible = "arm,armv8m-mpu"; |
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reg = <0xe000ed90 0x40>; |
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}; |
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}; |
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power-states { |
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/* This is the setting Sleep Mode */ |
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idle: idle { |
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compatible = "zephyr,power-state"; |
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power-state-name = "runtime-idle"; |
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min-residency-us = <0>; |
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exit-latency-us = <0>; |
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}; |
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/* This is the setting for Deep-sleep Mode */ |
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suspend: suspend { |
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compatible = "nxp,pdcfg-power", "zephyr,power-state"; |
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power-state-name = "suspend-to-idle"; |
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min-residency-us = <500>; |
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exit-latency-us = <120>; |
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/* |
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* These values are written to the PDSLEEPCFG |
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* registers to keep certain blocks such as |
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* LPOSC, SRAM's, FlexSPI0 SRAM powered on |
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* during deep sleep mode. |
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*/ |
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deep-sleep-config = <0xC800>, |
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<0x80000004>, |
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<0xFFFFFFFF>, |
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<0>; |
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}; |
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}; |
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}; |
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}; |
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&sram { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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/* RT5XX SRAM partitions are shared |
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* between code and data. Boards can |
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* override the reg properties of either sram0 or sram_code nodes to |
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* change the balance of SRAM allocation. |
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* |
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* Note that the sram code region starts at an offset of 0x1B000, |
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* as the boot ROM will not load code before 0x1C000. The first |
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* 0x1000 of the image will contain the boot header. |
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*/ |
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sram_code: memory@1b000 { |
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compatible = "mmio-sram"; |
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reg = <0x1b000 DT_SIZE_K(1428)>; |
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}; |
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sram0: memory@20180000 { |
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compatible = "mmio-sram"; |
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reg = <0x20180000 DT_SIZE_K(3072)>; |
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}; |
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sram1: memory@40140000 { |
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compatible = "zephyr,memory-region", "mmio-sram"; |
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reg = <0x40140000 DT_SIZE_K(16)>; |
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zephyr,memory-region = "SRAM1"; |
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zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; |
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}; |
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}; |
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&systick { |
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/* |
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* RT500 relies by default on the OS Timer for system clock |
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* implementation, so the SysTick node is not to be enabled. |
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*/ |
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status = "disabled"; |
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}; |
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&peripheral { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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/* |
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* Note that the offsets here are relative to the base address |
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* defined in either nxp_rt5xx_ns.dtsi or nxp_rt5xx.dtsi. The base |
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* addresses differ between non-secure (0x40000000) and secure |
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* modes (0x50000000). |
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*/ |
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clkctl0: clkctl@1000 { |
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compatible = "nxp,lpc-syscon"; |
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reg = <0x1000 0x1000>; |
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#clock-cells = <1>; |
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}; |
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iocon: iocon@4000 { |
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compatible = "nxp,lpc-iocon"; |
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reg = <0x4000 0x1000>; |
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pinctrl: pinctrl { |
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compatible = "nxp,rt-iocon-pinctrl"; |
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}; |
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}; |
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clkctl1: clkctl@21000 { |
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compatible = "nxp,lpc-syscon"; |
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reg = <0x21000 0x1000>; |
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#clock-cells = <1>; |
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}; |
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uuid: uuid@2f50 { |
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compatible = "nxp,lpc-uid"; |
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reg = <0x2f50 0x10>; |
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}; |
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gpio0: gpio@0 { |
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compatible = "nxp,lpc-gpio"; |
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reg = <0x100000 0x1000>; |
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int-source = "pint"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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port = <0>; |
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}; |
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gpio1: gpio@1 { |
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compatible = "nxp,lpc-gpio"; |
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reg = <0x100000 0x1000>; |
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int-source = "pint"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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port = <1>; |
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}; |
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gpio2: gpio@2 { |
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compatible = "nxp,lpc-gpio"; |
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reg = <0x100000 0x1000>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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port = <2>; |
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}; |
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gpio3: gpio@3 { |
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compatible = "nxp,lpc-gpio"; |
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reg = <0x100000 0x1000>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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port = <3>; |
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}; |
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gpio4: gpio@4 { |
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compatible = "nxp,lpc-gpio"; |
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reg = <0x100000 0x1000>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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port = <4>; |
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}; |
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gpio5: gpio@5 { |
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compatible = "nxp,lpc-gpio"; |
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reg = <0x100000 0x1000>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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port = <5>; |
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}; |
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gpio6: gpio@6 { |
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compatible = "nxp,lpc-gpio"; |
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reg = <0x100000 0x1000>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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port = <6>; |
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}; |
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pint: pint@25000 { |
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compatible = "nxp,pint"; |
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reg = <0x25000 0x1000>; |
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interrupt-controller; |
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#interrupt-cells = <1>; |
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#address-cells = <0>; |
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interrupts = <4 2>, <5 2>, <6 2>, <7 2>, |
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<35 2>, <36 2>, <37 2>, <38 2>; |
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num-lines = <8>; |
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num-inputs = <64>; |
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}; |
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flexcomm0: flexcomm@106000 { |
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compatible = "nxp,lpc-flexcomm"; |
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reg = <0x106000 0x1000>; |
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interrupts = <14 0>; |
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clocks = <&clkctl1 MCUX_FLEXCOMM0_CLK>; |
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status = "disabled"; |
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}; |
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flexcomm1: flexcomm@107000 { |
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compatible = "nxp,lpc-flexcomm"; |
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reg = <0x107000 0x1000>; |
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interrupts = <15 0>; |
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clocks = <&clkctl1 MCUX_FLEXCOMM1_CLK>; |
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status = "disabled"; |
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}; |
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flexcomm2: flexcomm@108000 { |
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compatible = "nxp,lpc-flexcomm"; |
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reg = <0x108000 0x1000>; |
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interrupts = <16 0>; |
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clocks = <&clkctl1 MCUX_FLEXCOMM2_CLK>; |
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status = "disabled"; |
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}; |
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flexcomm3: flexcomm@109000 { |
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compatible = "nxp,lpc-flexcomm"; |
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reg = <0x109000 0x1000>; |
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interrupts = <17 0>; |
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clocks = <&clkctl1 MCUX_FLEXCOMM3_CLK>; |
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status = "disabled"; |
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}; |
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flexcomm4: flexcomm@122000 { |
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compatible = "nxp,lpc-flexcomm"; |
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reg = <0x122000 0x1000>; |
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interrupts = <18 0>; |
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clocks = <&clkctl1 MCUX_FLEXCOMM4_CLK>; |
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status = "disabled"; |
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}; |
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flexcomm5: flexcomm@123000 { |
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compatible = "nxp,lpc-flexcomm"; |
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reg = <0x123000 0x1000>; |
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interrupts = <19 0>; |
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clocks = <&clkctl1 MCUX_FLEXCOMM5_CLK>; |
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status = "disabled"; |
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}; |
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flexcomm6: flexcomm@124000 { |
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compatible = "nxp,lpc-flexcomm"; |
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reg = <0x124000 0x1000>; |
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interrupts = <43 0>; |
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clocks = <&clkctl1 MCUX_FLEXCOMM6_CLK>; |
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status = "disabled"; |
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}; |
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flexcomm7: flexcomm@125000 { |
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compatible = "nxp,lpc-flexcomm"; |
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reg = <0x125000 0x1000>; |
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interrupts = <44 0>; |
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clocks = <&clkctl1 MCUX_FLEXCOMM7_CLK>; |
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status = "disabled"; |
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}; |
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pmic_i2c: i2c@127000 { |
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compatible = "nxp,lpc-i2c"; |
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reg = <0x127000 0x1000>; |
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interrupts = <21 0>; |
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clocks = <&clkctl1 MCUX_PMIC_I2C_CLK>; |
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status = "disabled"; |
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}; |
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flexcomm8: flexcomm@209000 { |
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compatible = "nxp,lpc-flexcomm"; |
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reg = <0x209000 0x1000>; |
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interrupts = <60 0>; |
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clocks = <&clkctl1 MCUX_FLEXCOMM8_CLK>; |
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status = "disabled"; |
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}; |
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flexcomm9: flexcomm@20a000 { |
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compatible = "nxp,lpc-flexcomm"; |
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reg = <0x20a000 0x1000>; |
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interrupts = <61 0>; |
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clocks = <&clkctl1 MCUX_FLEXCOMM9_CLK>; |
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status = "disabled"; |
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}; |
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flexcomm10: flexcomm@20b000 { |
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compatible = "nxp,lpc-flexcomm"; |
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reg = <0x20b000 0x1000>; |
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interrupts = <62 0>; |
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clocks = <&clkctl1 MCUX_FLEXCOMM10_CLK>; |
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status = "disabled"; |
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}; |
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flexcomm11: flexcomm@20c000 { |
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compatible = "nxp,lpc-flexcomm"; |
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reg = <0x20c000 0x1000>; |
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interrupts = <63 0>; |
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clocks = <&clkctl1 MCUX_FLEXCOMM11_CLK>; |
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status = "disabled"; |
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}; |
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flexcomm12: flexcomm@20d000 { |
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compatible = "nxp,lpc-flexcomm"; |
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reg = <0x20d000 0x1000>; |
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interrupts = <64 0>; |
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clocks = <&clkctl1 MCUX_FLEXCOMM12_CLK>; |
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status = "disabled"; |
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}; |
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flexcomm13: flexcomm@20e000 { |
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compatible = "nxp,lpc-flexcomm"; |
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reg = <0x20e000 0x1000>; |
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interrupts = <65 0>; |
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clocks = <&clkctl1 MCUX_FLEXCOMM13_CLK>; |
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status = "disabled"; |
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}; |
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lcdif: lcdif@210000 { |
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compatible = "nxp,dcnano-lcdif"; |
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reg = <0x210000 0x1000>; |
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interrupts = <69 0>; |
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status = "disabled"; |
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}; |
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usbhs: usbhs@144000 { |
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compatible = "nxp,lpcip3511"; |
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reg = <0x144000 0x1000>; |
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interrupts = <50 1>; |
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num-bidir-endpoints = <6>; |
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status = "disabled"; |
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}; |
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hs_lspi: spi@126000 { |
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compatible = "nxp,lpc-spi"; |
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reg = <0x126000 0x1000>; |
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interrupts = <20 0>; |
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clocks = <&clkctl1 MCUX_HS_SPI_CLK>; |
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status = "disabled"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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hs_lspi1: spi@128000 { |
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compatible = "nxp,lpc-spi"; |
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reg = <0x128000 0x1000>; |
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interrupts = <66 0>; |
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clocks = <&clkctl1 MCUX_HS_SPI1_CLK>; |
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status = "disabled"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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dma0: dma-controller@104000 { |
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compatible = "nxp,lpc-dma"; |
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reg = <0x104000 0x1000>; |
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interrupts = <1 0>; |
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dma-channels = <37>; |
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nxp,dma-num-of-otrigs = <4>; |
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nxp,dma-otrig-base-address = <RT595_DMA0_OTRIG_BASE>; |
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nxp,dma-itrig-base-address = <RT595_DMA0_ITRIG_BASE>; |
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status = "disabled"; |
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#dma-cells = <1>; |
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}; |
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dma1: dma-controller@105000 { |
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compatible = "nxp,lpc-dma"; |
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reg = <0x105000 0x1000>; |
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interrupts = <54 0>; |
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dma-channels = <37>; |
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nxp,dma-num-of-otrigs = <4>; |
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nxp,dma-otrig-base-address = <RT595_DMA1_OTRIG_BASE>; |
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nxp,dma-itrig-base-address = <RT595_DMA1_ITRIG_BASE>; |
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status = "disabled"; |
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#dma-cells = <1>; |
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}; |
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os_timer: timers@113000 { |
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compatible = "nxp,os-timer"; |
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reg = <0x113000 0x1000>; |
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interrupts = <41 0>; |
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status = "disabled"; |
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}; |
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rtc: rtc@30000 { |
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compatible = "nxp,lpc-rtc"; |
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reg = <0x30000 0x1000>; |
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interrupts = <32 0>; |
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status = "disabled"; |
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}; |
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trng: random@138000 { |
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compatible = "nxp,kinetis-trng"; |
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reg = <0x138000 0x1000>; |
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status = "okay"; |
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interrupts = <31 0>; |
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}; |
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sc_timer: pwm@146000 { |
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compatible = "nxp,sctimer-pwm"; |
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reg = <0x146000 0x1000>; |
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interrupts = <12 0>; |
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status = "disabled"; |
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prescaler = <8>; |
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#pwm-cells = <3>; |
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clocks = <&clkctl1 MCUX_SCTIMER_CLK>; |
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}; |
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wwdt0: watchdog@e000 { |
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compatible = "nxp,lpc-wwdt"; |
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reg = <0xe000 0x1000>; |
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interrupts = <0 0>; |
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status = "disabled"; |
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clk-divider = <1>; |
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}; |
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wwdt1: watchdog@2e000 { |
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compatible = "nxp,lpc-wwdt"; |
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reg = <0x2e000 0x1000>; |
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interrupts = <52 0>; |
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status = "disabled"; |
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clk-divider = <1>; |
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}; |
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usdhc0: usdhc@136000 { |
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compatible = "nxp,imx-usdhc"; |
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reg = <0x136000 0x1000>; |
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status = "disabled"; |
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interrupts = <45 0>; |
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clocks = <&clkctl1 MCUX_USDHC1_CLK>; |
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max-current-330 = <1020>; |
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max-current-180 = <1020>; |
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max-bus-freq = <208000000>; |
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min-bus-freq = <400000>; |
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}; |
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usdhc1: usdhc@137000 { |
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compatible = "nxp,imx-usdhc"; |
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reg = <0x137000 0x1000>; |
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status = "disabled"; |
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interrupts = <46 0>; |
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clocks = <&clkctl1 MCUX_USDHC2_CLK>; |
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max-current-330 = <1020>; |
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max-current-180 = <1020>; |
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max-bus-freq = <208000000>; |
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min-bus-freq = <400000>; |
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}; |
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lpadc0: lpadc@13A0000 { |
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compatible = "nxp,lpc-lpadc"; |
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reg = <0x13A000 0x304>; |
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interrupts = <22 0>; |
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status = "disabled"; |
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clk-divider = <1>; |
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clk-source = <0>; |
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voltage-ref= <1>; |
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calibration-average = <128>; |
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power-level = <0>; |
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offset-value-a = <10>; |
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offset-value-b = <10>; |
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#io-channel-cells = <1>; |
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}; |
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smartdma: dma@27020 { |
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compatible = "nxp,smartdma"; |
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reg = <0x27020 0x1000>; |
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program-mem = <0x24100000>; |
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interrupts = <73 0>; |
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status = "disabled"; |
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#dma-cells = <0>; |
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}; |
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ctimer0: ctimer@28000 { |
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compatible = "nxp,lpc-ctimer"; |
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reg = <0x28000 0x1000>; |
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interrupts = <10 0>; |
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status = "disabled"; |
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clk-source = <1>; |
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clocks = <&clkctl1 MCUX_CTIMER0_CLK>; |
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mode = <0>; |
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input = <0>; |
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prescale = <0>; |
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}; |
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ctimer1: ctimer@29000 { |
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compatible = "nxp,lpc-ctimer"; |
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reg = <0x29000 0x1000>; |
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interrupts = <11 0>; |
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status = "disabled"; |
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clk-source = <1>; |
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clocks = <&clkctl1 MCUX_CTIMER1_CLK>; |
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mode = <0>; |
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input = <0>; |
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prescale = <0>; |
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}; |
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ctimer2: ctimer@2a000 { |
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compatible = "nxp,lpc-ctimer"; |
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reg = <0x2a000 0x1000>; |
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interrupts = <39 0>; |
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status = "disabled"; |
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clk-source = <1>; |
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clocks = <&clkctl1 MCUX_CTIMER2_CLK>; |
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mode = <0>; |
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input = <0>; |
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prescale = <0>; |
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}; |
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ctimer3: ctimer@2b000 { |
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compatible = "nxp,lpc-ctimer"; |
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reg = <0x2b000 0x1000>; |
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interrupts = <13 0>; |
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status = "disabled"; |
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clk-source = <1>; |
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clocks = <&clkctl1 MCUX_CTIMER3_CLK>; |
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mode = <0>; |
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input = <0>; |
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prescale = <0>; |
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}; |
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ctimer4: ctimer@2c000 { |
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compatible = "nxp,lpc-ctimer"; |
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reg = <0x2c000 0x1000>; |
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interrupts = <40 0>; |
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status = "disabled"; |
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clk-source = <1>; |
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clocks = <&clkctl1 MCUX_CTIMER4_CLK>; |
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mode = <0>; |
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input = <0>; |
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prescale = <0>; |
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}; |
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mipi_dsi: mipi_dsi@31000 { |
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compatible = "nxp,mipi-dsi-2l"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x31000 0x1000>; |
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interrupts = <71 0>; |
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clocks = <&clkctl1 MCUX_MIPI_DSI_DPHY_CLK>, |
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<&clkctl1 MCUX_MIPI_DSI_ESC_CLK>, |
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<&clkctl1 MCUX_LCDIF_PIXEL_CLK>; |
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clock-names = "dphy", "esc", "pixel"; |
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status = "disabled"; |
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}; |
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i3c0: i3c@36000 { |
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compatible = "nxp,mcux-i3c"; |
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reg = <0x36000 0x1000>; |
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interrupts = <49 0>; |
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clocks = <&clkctl1 MCUX_I3C_CLK>; |
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clk-divider = <2>; |
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clk-divider-slow = <1>; |
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clk-divider-tc = <1>; |
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status = "disabled"; |
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#address-cells = <3>; |
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#size-cells = <0>; |
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}; |
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mbox:mbox@110000 { |
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compatible = "nxp,mbox-imx-mu"; |
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reg = <0x110000 0x100>; |
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interrupts = <34 0>; |
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rx-channels = <4>; |
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#mbox-cells = <1>; |
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status = "disabled"; |
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}; |
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mrt: mrt@2d000 { |
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compatible = "nxp,mrt"; |
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reg = <0x2d000 0x100>; |
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interrupts = <9 0>; |
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num-channels = <4>; |
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num-bits = <24>; |
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clocks = <&clkctl1 MCUX_MRT_CLK>; |
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#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
mrt_channel0: mrt_channel@0 { |
|
compatible = "nxp,mrt-channel"; |
|
reg = <0>; |
|
status = "disabled"; |
|
}; |
|
mrt_channel1: mrt_channel@1 { |
|
compatible = "nxp,mrt-channel"; |
|
reg = <1>; |
|
status = "disabled"; |
|
}; |
|
mrt_channel2: mrt_channel@2 { |
|
compatible = "nxp,mrt-channel"; |
|
reg = <2>; |
|
status = "disabled"; |
|
}; |
|
mrt_channel3: mrt_channel@3 { |
|
compatible = "nxp,mrt-channel"; |
|
reg = <3>; |
|
status = "disabled"; |
|
}; |
|
}; |
|
}; |
|
|
|
&flexspi { |
|
compatible = "nxp,imx-flexspi"; |
|
status = "disabled"; |
|
interrupts = <42 0>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
}; |
|
|
|
&flexspi2 { |
|
compatible = "nxp,imx-flexspi"; |
|
status = "disabled"; |
|
interrupts = <42 0>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
}; |
|
|
|
&nvic { |
|
arm,num-irq-priority-bits = <3>; |
|
};
|
|
|