Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.
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/*
* Copyright (c) 2022 Benjamin Björnsson <benjamin.bjornsson@gmail.com>.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
/ {
leds {
compatible = "gpio-leds";
red_led: led_0 {
gpios = <&gpiok 5 GPIO_ACTIVE_LOW>;
};
green_led: led_1 {
gpios = <&gpiok 6 GPIO_ACTIVE_LOW>;
};
blue_led: led_2 {
gpios = <&gpiok 7 GPIO_ACTIVE_LOW>;
};
};
otghs_ulpi_phy: otghs_ulpis_phy {
compatible = "usb-ulpi-phy";
reset-gpios = < &gpioj 4 GPIO_ACTIVE_LOW >;
#phy-cells = <0>;
};
aliases {
led0 = &red_led;
led1 = &green_led;
led2 = &blue_led;
};
};
&clk_hsi48 {
/* HSI48 required for USB */
status = "okay";
};
&rcc {
d1cpre = < 1 >;
hpre = < 2 >;
d1ppre = < 2 >;
d2ppre1 = < 2 >;
d2ppre2 = < 2 >;
d3ppre = < 2 >;
};
/* UART0 in datasheet */
&uart4 {
pinctrl-0 = <&uart4_tx_pa0 &uart4_rx_pi9>;
pinctrl-names = "default";
current-speed = <115200>;
};
/* UART1 in datasheet */
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
};
/* UART2 in datasheet */
&usart6 {
pinctrl-0 = <&usart6_tx_pg14 &usart6_rx_pg9>;
pinctrl-names = "default";
current-speed = <115200>;
};
/* UART3 in datasheet */
&uart8 {
pinctrl-0 = <&uart8_tx_pj8 &uart8_rx_pj9>;
pinctrl-names = "default";
current-speed = <115200>;
};
/* I2C0 in datasheet */
&i2c3 {
pinctrl-0 = <&i2c3_scl_ph7 &i2c3_sda_ph8>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_FAST>;
};
/* I2C1 in datasheet */
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_FAST>;
};
/* I2C2 in datasheet */
&i2c4 {
pinctrl-0 = <&i2c4_scl_ph11 &i2c4_sda_ph12>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_FAST>;
};
/* I2C3 in datasheet */
&i2c3 {
pinctrl-0 = <&i2c3_scl_ph7 &i2c3_sda_ph8>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_FAST>;
};
/* SPI1 in datasheet */
&spi2 {
pinctrl-0 = <&spi2_nss_pi0 &spi2_sck_pi1
&spi2_miso_pc2 &spi2_mosi_pc3>;
pinctrl-names = "default";
};
&fdcan1 {
pinctrl-0 = <&fdcan1_rx_pb8 &fdcan1_tx_ph13>;
pinctrl-names = "default";
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
<&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
};
&rtc {
status = "okay";
};
&mailbox {
status = "okay";
};
&fmc {
status = "okay";
pinctrl-0 = < &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d13_pd8 &fmc_d14_pd9
&fmc_d15_pd10 &fmc_d0_pd14 &fmc_d1_pd15 &fmc_nbl0_pe0
&fmc_nbl1_pe1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
&fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
&fmc_d11_pe14 &fmc_d12_pe15 &fmc_a0_pf0 &fmc_a1_pf1
&fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4 &fmc_a5_pf5
&fmc_sdnras_pf11 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
&fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1 &fmc_a12_pg2
&fmc_a14_pg4 /* FMC_BA0 */ &fmc_a15_pg5 /* FMC_BA1 */
&fmc_sdclk_pg8 &fmc_sdncas_pg15 &fmc_sdcke0_ph2 &fmc_sdne0_ph3
&fmc_sdnwe_ph5 >;
pinctrl-names = "default";
st,mem-swap = "disable";
sdram {
status = "okay";
mode-register = < 0x220 >;
/** From Arduino github repository:
* RefreshRate = 64 ms / 8192 cyc = 7.8125 us/cyc
* RefreshCycles = 7.8125 us * 90 MHz = 703
* According to the formula on p.1665 of the reference manual,
* we also need to subtract 20 from the value, so the target
* refresh rate is 703 - 20 = 683.
*/
refresh-rate = < 683 >;
num-auto-refresh = < 8 >;
bank@0 {
reg = < 0 >;
st,sdram-control = < STM32_FMC_SDRAM_NC_8
STM32_FMC_SDRAM_NR_12
STM32_FMC_SDRAM_MWID_16
STM32_FMC_SDRAM_NB_4
STM32_FMC_SDRAM_CAS_2
STM32_FMC_SDRAM_SDCLK_PERIOD_2
STM32_FMC_SDRAM_RBURST_ENABLE
STM32_FMC_SDRAM_RPIPE_0 >;
st,sdram-timing = < 2 7 5 7 2 3 3 >;
};
};
};
&quadspi {
pinctrl-0 = < &quadspi_bk1_io0_pd11
&quadspi_bk1_io1_pd12
&quadspi_bk1_io2_pf7
&quadspi_bk1_io3_pd13
&quadspi_bk1_ncs_pg6
&quadspi_clk_pf10 >;
pinctrl-names = "default";
status = "okay";
mx25l12833f: qspi-nor-flash@90000000 {
compatible = "st,stm32-qspi-nor";
reg = < 0x90000000 DT_SIZE_M(16) >; /* 128 MBits */
qspi-max-frequency = < 40000000 >;
sfdp-bfp = [ e5 20 f1 ff ff ff ff 07 44 eb 08 6b 08 3b 04 bb
fe ff ff ff ff ff 00 ff ff ff 44 eb 0c 20 0f 52
10 d8 00 ff 82 41 bd 00 81 e5 7b c6 44 03 67 38
30 b0 30 b0 f7 bd d5 5c 4a be 29 ff e1 d0 ff ff ];
jedec-id = [ 66 66 20 ];
spi-bus-width = <4>;
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = < 1 >;
#size-cells = < 1 >;
storage_partition: partition@0 {
label = "storage";
reg=< 0x0 DT_SIZE_K(15872) >;
};
wifi_firmware: partition@f80000 {
label = "wifi-firmware";
reg = < 0xf80000 DT_SIZE_K(512) >;
};
};
};
};
&rng {
status = "okay";
};
&mac {
pinctrl-0 = < &eth_ref_clk_pa1
&eth_crs_dv_pa7
&eth_rxd0_pc4
&eth_rxd1_pc5
&eth_tx_en_pg11
&eth_txd1_pg12
&eth_txd0_pg13 >;
pinctrl-names = "default";
phy-connection-type = "rmii";
status = "okay";
};
&mdio {
status = "okay";
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
status = "okay";
};
};
zephyr_udc0: &usbotg_hs {
pinctrl-0 = < &usb_otg_hs_ulpi_d0_pa3
&usb_otg_hs_ulpi_ck_pa5
&usb_otg_hs_ulpi_d1_pb0
&usb_otg_hs_ulpi_d2_pb1
&usb_otg_hs_ulpi_d7_pb5
&usb_otg_hs_ulpi_d3_pb10
&usb_otg_hs_ulpi_d4_pb11
&usb_otg_hs_ulpi_d5_pb12
&usb_otg_hs_ulpi_d6_pb13
&usb_otg_hs_ulpi_stp_pc0
&usb_otg_hs_ulpi_nxt_ph4
&usb_otg_hs_ulpi_dir_pi11 >;
pinctrl-names = "default";
phys = < &otghs_ulpi_phy >;
maximum-speed = "high-speed";
/* Include the USB1ULPIEN | USB1OTGHSULPIEN clock enable bit */
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x6000000>,
<&rcc STM32_SRC_HSI48 USB_SEL(3)>;
num-bidir-endpoints = < 4 >;
status = "okay";
};