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81 lines
2.3 KiB
81 lines
2.3 KiB
/* |
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* Copyright (c) 2025 Renesas Electronics Corporation |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT renesas_rx_icu |
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#include <zephyr/device.h> |
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#include <zephyr/irq.h> |
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#include <soc.h> |
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#include <zephyr/spinlock.h> |
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#include <zephyr/drivers/interrupt_controller/intc_rx_icu.h> |
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#include <zephyr/sw_isr_table.h> |
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#include <errno.h> |
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#define IR_BASE_ADDRESS DT_REG_ADDR_BY_NAME(DT_NODELABEL(icu), IR) |
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#define IRQCR_BASE_ADDRESS DT_REG_ADDR_BY_NAME(DT_NODELABEL(icu), IRQCR) |
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#define IRQFLTE_BASE_ADDRESS DT_REG_ADDR_BY_NAME(DT_NODELABEL(icu), IRQFLTE) |
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#define IRQFLTC0_BASE_ADDRESS DT_REG_ADDR_BY_NAME(DT_NODELABEL(icu), IRQFLTC0) |
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#define IRi_REG(i) (IR_BASE_ADDRESS + (i)) |
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#define IRQCRi_REG(i) (IRQCR_BASE_ADDRESS + (i)) |
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static struct k_spinlock lock; |
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void rx_icu_clear_ir_flag(unsigned int irqn) |
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{ |
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volatile uint8_t *icu_ir = (uint8_t *)IRi_REG(irqn); |
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/* Clear IR Register */ |
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*icu_ir = 0x0; |
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} |
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int rx_icu_get_ir_flag(unsigned int irqn) |
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{ |
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volatile uint8_t *icu_ir = (uint8_t *)IRi_REG(irqn); |
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/* Return IR Register */ |
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return *icu_ir; |
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} |
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int rx_icu_set_irq_control(unsigned int pin_irqn, enum icu_irq_mode mode) |
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{ |
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volatile uint8_t *icu_irqcr = (uint8_t *)IRQCRi_REG(pin_irqn); |
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if (mode >= ICU_MODE_NONE) { |
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return -EINVAL; |
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} |
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/* Set IRQ Control Register */ |
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*icu_irqcr = (uint8_t)(mode << 2); |
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return 0; |
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} |
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void rx_icu_set_irq_dig_filt(unsigned int pin_irqn, rx_irq_dig_filt_t dig_filt) |
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{ |
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volatile uint8_t *icu_irqflte = (uint8_t *)IRQFLTE_BASE_ADDRESS; |
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volatile uint16_t *icu_irqfltc0 = (uint16_t *)IRQFLTC0_BASE_ADDRESS; |
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uint8_t temp_8bit; |
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uint16_t temp_16bit; |
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k_spinlock_key_t key = k_spin_lock(&lock); |
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/* Set IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0) */ |
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temp_16bit = *icu_irqfltc0; |
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temp_16bit &= (uint16_t) ~(0x0003 << (pin_irqn * 2)); |
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temp_16bit |= ((uint16_t)(dig_filt.filt_clk_div) << (pin_irqn * 2)); |
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*icu_irqfltc0 = temp_16bit; |
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k_spin_unlock(&lock, key); |
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key = k_spin_lock(&lock); |
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/* Set IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0) */ |
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temp_8bit = *icu_irqflte; |
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temp_8bit &= (uint8_t) ~(1 << pin_irqn); |
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temp_8bit |= (uint8_t)(dig_filt.filt_enable << pin_irqn); |
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*icu_irqflte = temp_8bit; |
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k_spin_unlock(&lock, key); |
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} |
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DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, NULL, PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);
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