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158 lines
5.0 KiB
158 lines
5.0 KiB
/* |
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* Copyright (c) 2019-2021 Vestas Wind Systems A/S |
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* Copyright 2024 NXP |
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* |
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* Based on clock_control_mcux_sim.c, which is: |
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* Copyright (c) 2017, 2024 NXP |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT nxp_kinetis_scg |
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#include <zephyr/drivers/clock_control.h> |
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#include <zephyr/dt-bindings/clock/kinetis_scg.h> |
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#include <soc.h> |
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#include <fsl_clock.h> |
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#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL |
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#include <zephyr/logging/log.h> |
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LOG_MODULE_REGISTER(clock_control_scg); |
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#define MCUX_SCG_CLOCK_NODE(name) DT_INST_CHILD(0, name) |
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static int mcux_scg_on(const struct device *dev, |
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clock_control_subsys_t sub_system) |
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{ |
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return 0; |
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} |
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static int mcux_scg_off(const struct device *dev, |
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clock_control_subsys_t sub_system) |
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{ |
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return 0; |
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} |
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static int mcux_scg_get_rate(const struct device *dev, |
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clock_control_subsys_t sub_system, |
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uint32_t *rate) |
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{ |
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clock_name_t clock_name; |
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switch ((uint32_t) sub_system) { |
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case KINETIS_SCG_CORESYS_CLK: |
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clock_name = kCLOCK_CoreSysClk; |
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break; |
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case KINETIS_SCG_BUS_CLK: |
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clock_name = kCLOCK_BusClk; |
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break; |
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#if !(defined(CONFIG_SOC_MKE17Z7) || defined(CONFIG_SOC_MKE17Z9)) |
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case KINETIS_SCG_FLEXBUS_CLK: |
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clock_name = kCLOCK_FlexBusClk; |
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break; |
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#endif |
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case KINETIS_SCG_FLASH_CLK: |
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clock_name = kCLOCK_FlashClk; |
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break; |
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case KINETIS_SCG_SOSC_CLK: |
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clock_name = kCLOCK_ScgSysOscClk; |
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break; |
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case KINETIS_SCG_SIRC_CLK: |
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clock_name = kCLOCK_ScgSircClk; |
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break; |
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case KINETIS_SCG_FIRC_CLK: |
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clock_name = kCLOCK_ScgFircClk; |
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break; |
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#if (defined(FSL_FEATURE_SCG_HAS_SPLL) && FSL_FEATURE_SCG_HAS_SPLL) |
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case KINETIS_SCG_SPLL_CLK: |
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clock_name = kCLOCK_ScgSysPllClk; |
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break; |
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#endif /* (defined(FSL_FEATURE_SCG_HAS_SPLL) && FSL_FEATURE_SCG_HAS_SPLL) */ |
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#if (defined(FSL_FEATURE_SCG_HAS_LPFLL) && FSL_FEATURE_SCG_HAS_LPFLL) |
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case KINETIS_SCG_SPLL_CLK: |
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clock_name = kCLOCK_ScgLpFllClk; |
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break; |
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#endif /* (defined(FSL_FEATURE_SCG_HAS_LPFLL) && FSL_FEATURE_SCG_HAS_LPFLL) */ |
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#if (defined(FSL_FEATURE_SCG_HAS_SOSCDIV1) && FSL_FEATURE_SCG_HAS_SOSCDIV1) |
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case KINETIS_SCG_SOSC_ASYNC_DIV1_CLK: |
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clock_name = kCLOCK_ScgSysOscAsyncDiv1Clk; |
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break; |
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#endif /* (defined(FSL_FEATURE_SCG_HAS_SOSCDIV1) && FSL_FEATURE_SCG_HAS_SOSCDIV1) */ |
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case KINETIS_SCG_SOSC_ASYNC_DIV2_CLK: |
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clock_name = kCLOCK_ScgSysOscAsyncDiv2Clk; |
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break; |
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#if (defined(FSL_FEATURE_SCG_HAS_SIRCDIV1) && FSL_FEATURE_SCG_HAS_SIRCDIV1) |
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case KINETIS_SCG_SIRC_ASYNC_DIV1_CLK: |
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clock_name = kCLOCK_ScgSircAsyncDiv1Clk; |
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break; |
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#endif /* (defined(FSL_FEATURE_SCG_HAS_SIRCDIV1) && FSL_FEATURE_SCG_HAS_SIRCDIV1) */ |
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case KINETIS_SCG_SIRC_ASYNC_DIV2_CLK: |
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clock_name = kCLOCK_ScgSircAsyncDiv2Clk; |
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break; |
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#if (defined(FSL_FEATURE_FSL_FEATURE_SCG_HAS_FIRCDIV1) && FSL_FEATURE_SCG_HAS_FIRCDIV1) |
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case KINETIS_SCG_FIRC_ASYNC_DIV1_CLK: |
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clock_name = kCLOCK_ScgFircAsyncDiv1Clk; |
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break; |
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#endif /* (defined(FSL_FEATURE_FSL_FEATURE_SCG_HAS_FIRCDIV1) && FSL_FEATURE_SCG_HAS_FIRCDIV1) */ |
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case KINETIS_SCG_FIRC_ASYNC_DIV2_CLK: |
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clock_name = kCLOCK_ScgFircAsyncDiv2Clk; |
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break; |
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#if (defined(FSL_FEATURE_SCG_HAS_SPLLDIV1) && FSL_FEATURE_SCG_HAS_SPLLDIV1) |
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case KINETIS_SCG_SPLL_ASYNC_DIV1_CLK: |
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clock_name = kCLOCK_ScgSysPllAsyncDiv1Clk; |
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break; |
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#endif /* (defined(FSL_FEATURE_SCG_HAS_SPLLDIV1) && FSL_FEATURE_SCG_HAS_SPLLDIV1) */ |
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#if (defined(FSL_FEATURE_SCG_HAS_SPLL) && FSL_FEATURE_SCG_HAS_SPLL) |
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case KINETIS_SCG_SPLL_ASYNC_DIV2_CLK: |
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clock_name = kCLOCK_ScgSysPllAsyncDiv2Clk; |
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break; |
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#endif /* (defined(FSL_FEATURE_SCG_HAS_SPLL) && FSL_FEATURE_SCG_HAS_SPLL) */ |
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#if (defined(FSL_FEATURE_SCG_HAS_FLLDIV1) && FSL_FEATURE_SCG_HAS_FLLDIV1) |
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case KINETIS_SCG_LPFLL_ASYNC_DIV2_CLK: |
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clock_name = kCLOCK_ScgSysLPFllAsyncDiv2Clk; |
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break; |
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#endif /* (defined(FSL_FEATURE_SCG_HAS_FLLDIV1) && FSL_FEATURE_SCG_HAS_FLLDIV1) */ |
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default: |
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LOG_ERR("Unsupported clock name"); |
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return -EINVAL; |
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} |
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*rate = CLOCK_GetFreq(clock_name); |
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return 0; |
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} |
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static int mcux_scg_init(const struct device *dev) |
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{ |
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#if DT_NODE_HAS_STATUS_OKAY(MCUX_SCG_CLOCK_NODE(clkout_clk)) |
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#if DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(slow_clk)) |
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CLOCK_SetClkOutSel(kClockClkoutSelScgSlow); |
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#elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(sosc_clk)) |
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CLOCK_SetClkOutSel(kClockClkoutSelSysOsc); |
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#elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(sirc_clk)) |
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CLOCK_SetClkOutSel(kClockClkoutSelSirc); |
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#elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(firc_clk)) |
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CLOCK_SetClkOutSel(kClockClkoutSelFirc); |
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#elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(spll_clk)) |
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CLOCK_SetClkOutSel(kClockClkoutSelSysPll); |
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#else |
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#error Unsupported SCG clkout clock source |
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#endif |
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#endif /* DT_NODE_HAS_STATUS_OKAY(MCUX_SCG_CLOCK_NODE(clkout_clk)) */ |
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return 0; |
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} |
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static const struct clock_control_driver_api mcux_scg_driver_api = { |
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.on = mcux_scg_on, |
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.off = mcux_scg_off, |
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.get_rate = mcux_scg_get_rate, |
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}; |
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DEVICE_DT_INST_DEFINE(0, |
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mcux_scg_init, |
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NULL, |
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NULL, NULL, |
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PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, |
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&mcux_scg_driver_api);
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