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1315 lines
34 KiB
1315 lines
34 KiB
/* |
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* Copyright (c) 2016 BayLibre, SAS |
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* Copyright (c) 2017 Linaro Ltd |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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* |
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* I2C Driver for: STM32F0, STM32F3, STM32F7, STM32L0, STM32L4, STM32WB and |
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* STM32WL |
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* |
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*/ |
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|
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#include <zephyr/drivers/clock_control/stm32_clock_control.h> |
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#include <zephyr/drivers/clock_control.h> |
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#include <zephyr/sys/util.h> |
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#include <zephyr/kernel.h> |
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#include <soc.h> |
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#include <stm32_ll_i2c.h> |
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#include <errno.h> |
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#include <zephyr/drivers/i2c.h> |
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#include <zephyr/pm/device.h> |
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#include <zephyr/pm/device_runtime.h> |
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|
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#include <zephyr/cache.h> |
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#include <zephyr/linker/linker-defs.h> |
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#include <zephyr/mem_mgmt/mem_attr.h> |
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> |
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|
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#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL |
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#include <zephyr/logging/log.h> |
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LOG_MODULE_REGISTER(i2c_ll_stm32_v2); |
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|
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#include "i2c_ll_stm32.h" |
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#include "i2c-priv.h" |
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#define I2C_STM32_TRANSFER_TIMEOUT_MSEC 500 |
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|
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#ifdef CONFIG_I2C_STM32_V2_TIMING |
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/* Use the algorithm to calcuate the I2C timing */ |
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#ifndef I2C_STM32_VALID_TIMING_NBR |
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#define I2C_STM32_VALID_TIMING_NBR 128U |
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#endif |
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#define I2C_STM32_SPEED_FREQ_STANDARD 0U /* 100 kHz */ |
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#define I2C_STM32_SPEED_FREQ_FAST 1U /* 400 kHz */ |
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#define I2C_STM32_SPEED_FREQ_FAST_PLUS 2U /* 1 MHz */ |
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#define I2C_STM32_ANALOG_FILTER_DELAY_MIN 50U /* ns */ |
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#define I2C_STM32_ANALOG_FILTER_DELAY_MAX 260U /* ns */ |
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#define I2C_STM32_USE_ANALOG_FILTER 1U |
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#define I2C_STM32_DIGITAL_FILTER_COEF 0U |
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#define I2C_STM32_PRESC_MAX 16U |
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#define I2C_STM32_SCLDEL_MAX 16U |
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#define I2C_STM32_SDADEL_MAX 16U |
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#define I2C_STM32_SCLH_MAX 256U |
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#define I2C_STM32_SCLL_MAX 256U |
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/* I2C_DEVICE_Private_Types */ |
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struct i2c_stm32_charac_t { |
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uint32_t freq; /* Frequency in Hz */ |
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uint32_t freq_min; /* Minimum frequency in Hz */ |
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uint32_t freq_max; /* Maximum frequency in Hz */ |
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uint32_t hddat_min; /* Minimum data hold time in ns */ |
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uint32_t vddat_max; /* Maximum data valid time in ns */ |
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uint32_t sudat_min; /* Minimum data setup time in ns */ |
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uint32_t lscl_min; /* Minimum low period of the SCL clock in ns */ |
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uint32_t hscl_min; /* Minimum high period of SCL clock in ns */ |
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uint32_t trise; /* Rise time in ns */ |
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uint32_t tfall; /* Fall time in ns */ |
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uint32_t dnf; /* Digital noise filter coefficient */ |
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}; |
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struct i2c_stm32_timings_t { |
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uint32_t presc; /* Timing prescaler */ |
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uint32_t tscldel; /* SCL delay */ |
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uint32_t tsdadel; /* SDA delay */ |
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uint32_t sclh; /* SCL high period */ |
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uint32_t scll; /* SCL low period */ |
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}; |
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|
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/* I2C_DEVICE Private Constants */ |
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static const struct i2c_stm32_charac_t i2c_stm32_charac[] = { |
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[I2C_STM32_SPEED_FREQ_STANDARD] = { |
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.freq = 100000, |
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.freq_min = 80000, |
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.freq_max = 120000, |
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.hddat_min = 0, |
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.vddat_max = 3450, |
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.sudat_min = 250, |
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.lscl_min = 4700, |
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.hscl_min = 4000, |
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.trise = 640, |
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.tfall = 20, |
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.dnf = I2C_STM32_DIGITAL_FILTER_COEF, |
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}, |
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[I2C_STM32_SPEED_FREQ_FAST] = { |
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.freq = 400000, |
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.freq_min = 320000, |
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.freq_max = 480000, |
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.hddat_min = 0, |
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.vddat_max = 900, |
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.sudat_min = 100, |
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.lscl_min = 1300, |
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.hscl_min = 600, |
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.trise = 250, |
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.tfall = 100, |
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.dnf = I2C_STM32_DIGITAL_FILTER_COEF, |
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}, |
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[I2C_STM32_SPEED_FREQ_FAST_PLUS] = { |
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.freq = 1000000, |
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.freq_min = 800000, |
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.freq_max = 1200000, |
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.hddat_min = 0, |
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.vddat_max = 450, |
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.sudat_min = 50, |
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.lscl_min = 500, |
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.hscl_min = 260, |
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.trise = 60, |
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.tfall = 100, |
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.dnf = I2C_STM32_DIGITAL_FILTER_COEF, |
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}, |
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}; |
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static struct i2c_stm32_timings_t i2c_valid_timing[I2C_STM32_VALID_TIMING_NBR]; |
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static uint32_t i2c_valid_timing_nbr; |
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#endif /* CONFIG_I2C_STM32_V2_TIMING */ |
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#ifdef CONFIG_I2C_STM32_V2_DMA |
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static int configure_dma(struct stream const *dma, struct dma_config *dma_cfg, |
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struct dma_block_config *blk_cfg) |
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{ |
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if (!device_is_ready(dma->dev_dma)) { |
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LOG_ERR("DMA device not ready"); |
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return -ENODEV; |
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} |
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dma_cfg->head_block = blk_cfg; |
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dma_cfg->block_count = 1; |
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int ret = dma_config(dma->dev_dma, dma->dma_channel, dma_cfg); |
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if (ret != 0) { |
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LOG_ERR("Problem setting up DMA: %d", ret); |
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return ret; |
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} |
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ret = dma_start(dma->dev_dma, dma->dma_channel); |
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if (ret != 0) { |
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LOG_ERR("Problem starting DMA: %d", ret); |
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return ret; |
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} |
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return 0; |
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} |
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#endif /* CONFIG_I2C_STM32_V2_DMA */ |
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static inline void msg_init(const struct device *dev, struct i2c_msg *msg, |
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uint8_t *next_msg_flags, uint16_t slave, |
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uint32_t transfer) |
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{ |
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const struct i2c_stm32_config *cfg = dev->config; |
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struct i2c_stm32_data *data = dev->data; |
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I2C_TypeDef *i2c = cfg->i2c; |
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|
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if (LL_I2C_IsEnabledReloadMode(i2c)) { |
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LL_I2C_SetTransferSize(i2c, msg->len); |
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} else { |
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if (I2C_ADDR_10_BITS & data->dev_config) { |
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LL_I2C_SetMasterAddressingMode(i2c, |
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LL_I2C_ADDRESSING_MODE_10BIT); |
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LL_I2C_SetSlaveAddr(i2c, (uint32_t) slave); |
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} else { |
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LL_I2C_SetMasterAddressingMode(i2c, |
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LL_I2C_ADDRESSING_MODE_7BIT); |
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LL_I2C_SetSlaveAddr(i2c, (uint32_t) slave << 1); |
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} |
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|
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if (!(msg->flags & I2C_MSG_STOP) && next_msg_flags && |
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!(*next_msg_flags & I2C_MSG_RESTART)) { |
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LL_I2C_EnableReloadMode(i2c); |
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} else { |
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LL_I2C_DisableReloadMode(i2c); |
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} |
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LL_I2C_DisableAutoEndMode(i2c); |
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LL_I2C_SetTransferRequest(i2c, transfer); |
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LL_I2C_SetTransferSize(i2c, msg->len); |
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#if defined(CONFIG_I2C_TARGET) |
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data->master_active = true; |
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#endif |
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#ifdef CONFIG_I2C_STM32_V2_DMA |
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if (msg->len) { |
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if (msg->flags & I2C_MSG_READ) { |
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/* Configure RX DMA */ |
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data->dma_blk_cfg.source_address = LL_I2C_DMA_GetRegAddr( |
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cfg->i2c, LL_I2C_DMA_REG_DATA_RECEIVE); |
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data->dma_blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; |
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data->dma_blk_cfg.dest_address = (uint32_t)msg->buf; |
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data->dma_blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; |
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data->dma_blk_cfg.block_size = msg->len; |
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|
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if (configure_dma(&cfg->rx_dma, &data->dma_rx_cfg, |
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&data->dma_blk_cfg) != 0) { |
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LOG_ERR("Problem setting up RX DMA"); |
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return; |
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} |
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data->current.buf += msg->len; |
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data->current.len -= msg->len; |
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LL_I2C_EnableDMAReq_RX(i2c); |
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} else { |
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if (data->current.len) { |
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/* Configure TX DMA */ |
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data->dma_blk_cfg.source_address = |
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(uint32_t)data->current.buf; |
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data->dma_blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT; |
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data->dma_blk_cfg.dest_address = LL_I2C_DMA_GetRegAddr( |
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cfg->i2c, LL_I2C_DMA_REG_DATA_TRANSMIT); |
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data->dma_blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; |
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data->dma_blk_cfg.block_size = msg->len; |
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if (configure_dma(&cfg->tx_dma, &data->dma_tx_cfg, |
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&data->dma_blk_cfg) != 0) { |
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LOG_ERR("Problem setting up TX DMA"); |
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return; |
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} |
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data->current.buf += data->current.len; |
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data->current.len -= data->current.len; |
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LL_I2C_EnableDMAReq_TX(i2c); |
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} |
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} |
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} |
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#endif /* CONFIG_I2C_STM32_V2_DMA */ |
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LL_I2C_Enable(i2c); |
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LL_I2C_GenerateStartCondition(i2c); |
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} |
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} |
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#ifdef CONFIG_I2C_STM32_INTERRUPT |
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static void i2c_stm32_disable_transfer_interrupts(const struct device *dev) |
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{ |
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const struct i2c_stm32_config *cfg = dev->config; |
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struct i2c_stm32_data *data = dev->data; |
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I2C_TypeDef *i2c = cfg->i2c; |
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LL_I2C_DisableIT_TX(i2c); |
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LL_I2C_DisableIT_RX(i2c); |
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LL_I2C_DisableIT_STOP(i2c); |
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LL_I2C_DisableIT_NACK(i2c); |
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LL_I2C_DisableIT_TC(i2c); |
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if (!data->smbalert_active) { |
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LL_I2C_DisableIT_ERR(i2c); |
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} |
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} |
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static void i2c_stm32_enable_transfer_interrupts(const struct device *dev) |
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{ |
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const struct i2c_stm32_config *cfg = dev->config; |
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I2C_TypeDef *i2c = cfg->i2c; |
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LL_I2C_EnableIT_STOP(i2c); |
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LL_I2C_EnableIT_NACK(i2c); |
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LL_I2C_EnableIT_TC(i2c); |
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LL_I2C_EnableIT_ERR(i2c); |
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} |
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static void i2c_stm32_master_mode_end(const struct device *dev) |
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{ |
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const struct i2c_stm32_config *cfg = dev->config; |
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struct i2c_stm32_data *data = dev->data; |
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I2C_TypeDef *i2c = cfg->i2c; |
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i2c_stm32_disable_transfer_interrupts(dev); |
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if (LL_I2C_IsEnabledReloadMode(i2c)) { |
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LL_I2C_DisableReloadMode(i2c); |
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} |
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#if defined(CONFIG_I2C_TARGET) |
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data->master_active = false; |
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if (!data->slave_attached && !data->smbalert_active) { |
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LL_I2C_Disable(i2c); |
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} |
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#else |
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if (!data->smbalert_active) { |
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LL_I2C_Disable(i2c); |
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} |
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#endif |
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#ifdef CONFIG_I2C_STM32_V2_DMA |
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if (data->current.msg->flags & I2C_MSG_READ) { |
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dma_stop(cfg->rx_dma.dev_dma, cfg->rx_dma.dma_channel); |
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LL_I2C_DisableDMAReq_RX(i2c); |
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} else { |
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dma_stop(cfg->tx_dma.dev_dma, cfg->tx_dma.dma_channel); |
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LL_I2C_DisableDMAReq_TX(i2c); |
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} |
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#endif /* CONFIG_I2C_STM32_V2_DMA */ |
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k_sem_give(&data->device_sync_sem); |
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} |
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|
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#if defined(CONFIG_I2C_TARGET) |
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static void i2c_stm32_slave_event(const struct device *dev) |
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{ |
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const struct i2c_stm32_config *cfg = dev->config; |
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struct i2c_stm32_data *data = dev->data; |
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I2C_TypeDef *i2c = cfg->i2c; |
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const struct i2c_target_callbacks *slave_cb; |
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struct i2c_target_config *slave_cfg; |
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if (data->slave_cfg->flags != I2C_TARGET_FLAGS_ADDR_10_BITS) { |
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uint8_t slave_address; |
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|
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/* Choose the right slave from the address match code */ |
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slave_address = LL_I2C_GetAddressMatchCode(i2c) >> 1; |
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if (data->slave_cfg != NULL && |
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slave_address == data->slave_cfg->address) { |
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slave_cfg = data->slave_cfg; |
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} else if (data->slave2_cfg != NULL && |
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slave_address == data->slave2_cfg->address) { |
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slave_cfg = data->slave2_cfg; |
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} else { |
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__ASSERT_NO_MSG(0); |
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return; |
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} |
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} else { |
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/* On STM32 the LL_I2C_GetAddressMatchCode & (ISR register) returns |
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* only 7bits of address match so 10 bit dual addressing is broken. |
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* Revert to assuming single address match. |
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*/ |
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if (data->slave_cfg != NULL) { |
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slave_cfg = data->slave_cfg; |
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} else { |
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__ASSERT_NO_MSG(0); |
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return; |
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} |
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} |
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slave_cb = slave_cfg->callbacks; |
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|
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if (LL_I2C_IsActiveFlag_TXIS(i2c)) { |
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uint8_t val; |
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|
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if (slave_cb->read_processed(slave_cfg, &val) < 0) { |
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LOG_ERR("Error continuing reading"); |
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} else { |
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LL_I2C_TransmitData8(i2c, val); |
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} |
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return; |
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} |
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|
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if (LL_I2C_IsActiveFlag_RXNE(i2c)) { |
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uint8_t val = LL_I2C_ReceiveData8(i2c); |
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|
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if (slave_cb->write_received(slave_cfg, val)) { |
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LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK); |
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} |
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return; |
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} |
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|
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if (LL_I2C_IsActiveFlag_NACK(i2c)) { |
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LL_I2C_ClearFlag_NACK(i2c); |
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} |
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if (LL_I2C_IsActiveFlag_STOP(i2c)) { |
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i2c_stm32_disable_transfer_interrupts(dev); |
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|
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/* Flush remaining TX byte before clearing Stop Flag */ |
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LL_I2C_ClearFlag_TXE(i2c); |
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LL_I2C_ClearFlag_STOP(i2c); |
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slave_cb->stop(slave_cfg); |
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|
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/* Prepare to ACK next transmissions address byte */ |
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LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK); |
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} |
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|
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if (LL_I2C_IsActiveFlag_ADDR(i2c)) { |
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uint32_t dir; |
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|
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LL_I2C_ClearFlag_ADDR(i2c); |
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|
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dir = LL_I2C_GetTransferDirection(i2c); |
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if (dir == LL_I2C_DIRECTION_WRITE) { |
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if (slave_cb->write_requested(slave_cfg) < 0) { |
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LOG_ERR("Error initiating writing"); |
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} else { |
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LL_I2C_EnableIT_RX(i2c); |
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} |
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} else { |
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uint8_t val; |
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|
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if (slave_cb->read_requested(slave_cfg, &val) < 0) { |
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LOG_ERR("Error initiating reading"); |
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} else { |
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LL_I2C_TransmitData8(i2c, val); |
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LL_I2C_EnableIT_TX(i2c); |
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} |
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} |
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|
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i2c_stm32_enable_transfer_interrupts(dev); |
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} |
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} |
|
|
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/* Attach and start I2C as target */ |
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int i2c_stm32_target_register(const struct device *dev, |
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struct i2c_target_config *config) |
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{ |
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const struct i2c_stm32_config *cfg = dev->config; |
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struct i2c_stm32_data *data = dev->data; |
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I2C_TypeDef *i2c = cfg->i2c; |
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uint32_t bitrate_cfg; |
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int ret; |
|
|
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if (!config) { |
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return -EINVAL; |
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} |
|
|
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if (data->slave_cfg && data->slave2_cfg) { |
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return -EBUSY; |
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} |
|
|
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if (data->master_active) { |
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return -EBUSY; |
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} |
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|
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bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate); |
|
|
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ret = i2c_stm32_runtime_configure(dev, bitrate_cfg); |
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if (ret < 0) { |
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LOG_ERR("i2c: failure initializing"); |
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return ret; |
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} |
|
|
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/* Mark device as active */ |
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(void)pm_device_runtime_get(dev); |
|
|
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if (pm_device_wakeup_is_capable(dev)) { |
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/* Enable wake-up from stop */ |
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LOG_DBG("i2c: enabling wakeup from stop"); |
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LL_I2C_EnableWakeUpFromStop(cfg->i2c); |
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} |
|
|
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LL_I2C_Enable(i2c); |
|
|
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if (!data->slave_cfg) { |
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data->slave_cfg = config; |
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if (data->slave_cfg->flags == I2C_TARGET_FLAGS_ADDR_10_BITS) { |
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LL_I2C_SetOwnAddress1(i2c, config->address, LL_I2C_OWNADDRESS1_10BIT); |
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LOG_DBG("i2c: target #1 registered with 10-bit address"); |
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} else { |
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LL_I2C_SetOwnAddress1(i2c, config->address << 1U, LL_I2C_OWNADDRESS1_7BIT); |
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LOG_DBG("i2c: target #1 registered with 7-bit address"); |
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} |
|
|
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LL_I2C_EnableOwnAddress1(i2c); |
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|
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LOG_DBG("i2c: target #1 registered"); |
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} else { |
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data->slave2_cfg = config; |
|
|
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if (data->slave2_cfg->flags == I2C_TARGET_FLAGS_ADDR_10_BITS) { |
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return -EINVAL; |
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} |
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LL_I2C_SetOwnAddress2(i2c, config->address << 1U, |
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LL_I2C_OWNADDRESS2_NOMASK); |
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LL_I2C_EnableOwnAddress2(i2c); |
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LOG_DBG("i2c: target #2 registered"); |
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} |
|
|
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data->slave_attached = true; |
|
|
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LL_I2C_EnableIT_ADDR(i2c); |
|
|
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return 0; |
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} |
|
|
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int i2c_stm32_target_unregister(const struct device *dev, |
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struct i2c_target_config *config) |
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{ |
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const struct i2c_stm32_config *cfg = dev->config; |
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struct i2c_stm32_data *data = dev->data; |
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I2C_TypeDef *i2c = cfg->i2c; |
|
|
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if (!data->slave_attached) { |
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return -EINVAL; |
|
} |
|
|
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if (data->master_active) { |
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return -EBUSY; |
|
} |
|
|
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if (config == data->slave_cfg) { |
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LL_I2C_DisableOwnAddress1(i2c); |
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data->slave_cfg = NULL; |
|
|
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LOG_DBG("i2c: slave #1 unregistered"); |
|
} else if (config == data->slave2_cfg) { |
|
LL_I2C_DisableOwnAddress2(i2c); |
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data->slave2_cfg = NULL; |
|
|
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LOG_DBG("i2c: slave #2 unregistered"); |
|
} else { |
|
return -EINVAL; |
|
} |
|
|
|
/* Return if there is a slave remaining */ |
|
if (data->slave_cfg || data->slave2_cfg) { |
|
LOG_DBG("i2c: target#%c still registered", data->slave_cfg?'1':'2'); |
|
return 0; |
|
} |
|
|
|
/* Otherwise disable I2C */ |
|
LL_I2C_DisableIT_ADDR(i2c); |
|
i2c_stm32_disable_transfer_interrupts(dev); |
|
|
|
LL_I2C_ClearFlag_NACK(i2c); |
|
LL_I2C_ClearFlag_STOP(i2c); |
|
LL_I2C_ClearFlag_ADDR(i2c); |
|
|
|
if (!data->smbalert_active) { |
|
LL_I2C_Disable(i2c); |
|
} |
|
|
|
if (pm_device_wakeup_is_capable(dev)) { |
|
/* Disable wake-up from STOP */ |
|
LOG_DBG("i2c: disabling wakeup from stop"); |
|
LL_I2C_DisableWakeUpFromStop(i2c); |
|
} |
|
|
|
/* Release the device */ |
|
(void)pm_device_runtime_put(dev); |
|
|
|
data->slave_attached = false; |
|
|
|
return 0; |
|
} |
|
|
|
#endif /* defined(CONFIG_I2C_TARGET) */ |
|
|
|
void i2c_stm32_event(const struct device *dev) |
|
{ |
|
const struct i2c_stm32_config *cfg = dev->config; |
|
struct i2c_stm32_data *data = dev->data; |
|
I2C_TypeDef *i2c = cfg->i2c; |
|
|
|
#if defined(CONFIG_I2C_TARGET) |
|
if (data->slave_attached && !data->master_active) { |
|
i2c_stm32_slave_event(dev); |
|
return; |
|
} |
|
#endif |
|
if (data->current.len) { |
|
/* Send next byte */ |
|
if (LL_I2C_IsActiveFlag_TXIS(i2c)) { |
|
LL_I2C_TransmitData8(i2c, *data->current.buf); |
|
} |
|
|
|
/* Receive next byte */ |
|
if (LL_I2C_IsActiveFlag_RXNE(i2c)) { |
|
*data->current.buf = LL_I2C_ReceiveData8(i2c); |
|
} |
|
|
|
data->current.buf++; |
|
data->current.len--; |
|
} |
|
|
|
/* NACK received */ |
|
if (LL_I2C_IsActiveFlag_NACK(i2c)) { |
|
LL_I2C_ClearFlag_NACK(i2c); |
|
data->current.is_nack = 1U; |
|
/* |
|
* AutoEndMode is always disabled in master mode, |
|
* so send a stop condition manually |
|
*/ |
|
LL_I2C_GenerateStopCondition(i2c); |
|
return; |
|
} |
|
|
|
/* STOP received */ |
|
if (LL_I2C_IsActiveFlag_STOP(i2c)) { |
|
LL_I2C_ClearFlag_STOP(i2c); |
|
LL_I2C_DisableReloadMode(i2c); |
|
goto end; |
|
} |
|
|
|
/* Transfer Complete or Transfer Complete Reload */ |
|
if (LL_I2C_IsActiveFlag_TC(i2c) || |
|
LL_I2C_IsActiveFlag_TCR(i2c)) { |
|
/* Issue stop condition if necessary */ |
|
if (data->current.msg->flags & I2C_MSG_STOP) { |
|
LL_I2C_GenerateStopCondition(i2c); |
|
} else { |
|
i2c_stm32_disable_transfer_interrupts(dev); |
|
|
|
#ifdef CONFIG_I2C_STM32_V2_DMA |
|
if (data->current.msg->flags & I2C_MSG_READ) { |
|
dma_stop(cfg->rx_dma.dev_dma, cfg->rx_dma.dma_channel); |
|
LL_I2C_DisableDMAReq_RX(i2c); |
|
} else { |
|
dma_stop(cfg->tx_dma.dev_dma, cfg->tx_dma.dma_channel); |
|
LL_I2C_DisableDMAReq_TX(i2c); |
|
} |
|
#endif /* CONFIG_I2C_STM32_V2_DMA */ |
|
|
|
k_sem_give(&data->device_sync_sem); |
|
} |
|
} |
|
|
|
return; |
|
end: |
|
i2c_stm32_master_mode_end(dev); |
|
} |
|
|
|
int i2c_stm32_error(const struct device *dev) |
|
{ |
|
const struct i2c_stm32_config *cfg = dev->config; |
|
struct i2c_stm32_data *data = dev->data; |
|
I2C_TypeDef *i2c = cfg->i2c; |
|
|
|
#if defined(CONFIG_I2C_TARGET) |
|
if (data->slave_attached && !data->master_active) { |
|
/* No need for a slave error function right now. */ |
|
return 0; |
|
} |
|
#endif |
|
|
|
if (LL_I2C_IsActiveFlag_ARLO(i2c)) { |
|
LL_I2C_ClearFlag_ARLO(i2c); |
|
data->current.is_arlo = 1U; |
|
goto end; |
|
} |
|
|
|
if (LL_I2C_IsActiveFlag_BERR(i2c)) { |
|
LL_I2C_ClearFlag_BERR(i2c); |
|
data->current.is_err = 1U; |
|
goto end; |
|
} |
|
|
|
#if defined(CONFIG_SMBUS_STM32_SMBALERT) |
|
if (LL_I2C_IsActiveSMBusFlag_ALERT(i2c)) { |
|
LL_I2C_ClearSMBusFlag_ALERT(i2c); |
|
if (data->smbalert_cb_func != NULL) { |
|
data->smbalert_cb_func(data->smbalert_cb_dev); |
|
} |
|
goto end; |
|
} |
|
#endif |
|
|
|
return 0; |
|
end: |
|
i2c_stm32_master_mode_end(dev); |
|
return -EIO; |
|
} |
|
|
|
static int i2c_stm32_msg_write(const struct device *dev, struct i2c_msg *msg, |
|
uint8_t *next_msg_flags, uint16_t slave) |
|
{ |
|
const struct i2c_stm32_config *cfg = dev->config; |
|
struct i2c_stm32_data *data = dev->data; |
|
I2C_TypeDef *i2c = cfg->i2c; |
|
bool is_timeout = false; |
|
|
|
data->current.len = msg->len; |
|
data->current.buf = msg->buf; |
|
data->current.is_write = 1U; |
|
data->current.is_nack = 0U; |
|
data->current.is_err = 0U; |
|
data->current.msg = msg; |
|
|
|
#if defined(CONFIG_I2C_STM32_V2_DMA) |
|
if (!stm32_buf_in_nocache((uintptr_t)msg->buf, msg->len)) { |
|
LOG_DBG("Tx buffer at %p (len %zu) is in cached memory; cleaning cache", msg->buf, |
|
msg->len); |
|
sys_cache_data_flush_range((void *)msg->buf, msg->len); |
|
} |
|
#endif /* CONFIG_I2C_STM32_V2_DMA */ |
|
|
|
msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_WRITE); |
|
|
|
i2c_stm32_enable_transfer_interrupts(dev); |
|
LL_I2C_EnableIT_TX(i2c); |
|
|
|
if (k_sem_take(&data->device_sync_sem, |
|
K_MSEC(I2C_STM32_TRANSFER_TIMEOUT_MSEC)) != 0) { |
|
i2c_stm32_master_mode_end(dev); |
|
k_sem_take(&data->device_sync_sem, K_FOREVER); |
|
is_timeout = true; |
|
} |
|
|
|
if (data->current.is_nack || data->current.is_err || |
|
data->current.is_arlo || is_timeout) { |
|
goto error; |
|
} |
|
|
|
return 0; |
|
error: |
|
if (data->current.is_arlo) { |
|
LOG_DBG("%s: ARLO %d", __func__, |
|
data->current.is_arlo); |
|
data->current.is_arlo = 0U; |
|
} |
|
|
|
if (data->current.is_nack) { |
|
LOG_DBG("%s: NACK", __func__); |
|
data->current.is_nack = 0U; |
|
} |
|
|
|
if (data->current.is_err) { |
|
LOG_DBG("%s: ERR %d", __func__, |
|
data->current.is_err); |
|
data->current.is_err = 0U; |
|
} |
|
|
|
if (is_timeout) { |
|
LOG_DBG("%s: TIMEOUT", __func__); |
|
} |
|
|
|
return -EIO; |
|
} |
|
|
|
static int i2c_stm32_msg_read(const struct device *dev, struct i2c_msg *msg, |
|
uint8_t *next_msg_flags, uint16_t slave) |
|
{ |
|
const struct i2c_stm32_config *cfg = dev->config; |
|
struct i2c_stm32_data *data = dev->data; |
|
I2C_TypeDef *i2c = cfg->i2c; |
|
bool is_timeout = false; |
|
|
|
data->current.len = msg->len; |
|
data->current.buf = msg->buf; |
|
data->current.is_write = 0U; |
|
data->current.is_arlo = 0U; |
|
data->current.is_err = 0U; |
|
data->current.is_nack = 0U; |
|
data->current.msg = msg; |
|
|
|
msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_READ); |
|
|
|
i2c_stm32_enable_transfer_interrupts(dev); |
|
LL_I2C_EnableIT_RX(i2c); |
|
|
|
if (k_sem_take(&data->device_sync_sem, |
|
K_MSEC(I2C_STM32_TRANSFER_TIMEOUT_MSEC)) != 0) { |
|
i2c_stm32_master_mode_end(dev); |
|
k_sem_take(&data->device_sync_sem, K_FOREVER); |
|
is_timeout = true; |
|
} |
|
#if defined(CONFIG_I2C_STM32_V2_DMA) |
|
if (!stm32_buf_in_nocache((uintptr_t)msg->buf, msg->len)) { |
|
LOG_DBG("Rx buffer at %p (len %zu) is in cached memory; invalidating cache", |
|
msg->buf, msg->len); |
|
sys_cache_data_invd_range((void *)msg->buf, msg->len); |
|
} |
|
#endif /* CONFIG_I2C_STM32_V2_DMA */ |
|
|
|
if (data->current.is_nack || data->current.is_err || |
|
data->current.is_arlo || is_timeout) { |
|
goto error; |
|
} |
|
|
|
return 0; |
|
error: |
|
if (data->current.is_arlo) { |
|
LOG_DBG("%s: ARLO %d", __func__, |
|
data->current.is_arlo); |
|
data->current.is_arlo = 0U; |
|
} |
|
|
|
if (data->current.is_nack) { |
|
LOG_DBG("%s: NACK", __func__); |
|
data->current.is_nack = 0U; |
|
} |
|
|
|
if (data->current.is_err) { |
|
LOG_DBG("%s: ERR %d", __func__, |
|
data->current.is_err); |
|
data->current.is_err = 0U; |
|
} |
|
|
|
if (is_timeout) { |
|
LOG_DBG("%s: TIMEOUT", __func__); |
|
} |
|
|
|
return -EIO; |
|
} |
|
|
|
#else /* !CONFIG_I2C_STM32_INTERRUPT */ |
|
static inline int check_errors(const struct device *dev, const char *funcname) |
|
{ |
|
const struct i2c_stm32_config *cfg = dev->config; |
|
I2C_TypeDef *i2c = cfg->i2c; |
|
|
|
if (LL_I2C_IsActiveFlag_NACK(i2c)) { |
|
LL_I2C_ClearFlag_NACK(i2c); |
|
LOG_DBG("%s: NACK", funcname); |
|
goto error; |
|
} |
|
|
|
if (LL_I2C_IsActiveFlag_ARLO(i2c)) { |
|
LL_I2C_ClearFlag_ARLO(i2c); |
|
LOG_DBG("%s: ARLO", funcname); |
|
goto error; |
|
} |
|
|
|
if (LL_I2C_IsActiveFlag_OVR(i2c)) { |
|
LL_I2C_ClearFlag_OVR(i2c); |
|
LOG_DBG("%s: OVR", funcname); |
|
goto error; |
|
} |
|
|
|
if (LL_I2C_IsActiveFlag_BERR(i2c)) { |
|
LL_I2C_ClearFlag_BERR(i2c); |
|
LOG_DBG("%s: BERR", funcname); |
|
goto error; |
|
} |
|
|
|
return 0; |
|
error: |
|
if (LL_I2C_IsEnabledReloadMode(i2c)) { |
|
LL_I2C_DisableReloadMode(i2c); |
|
} |
|
return -EIO; |
|
} |
|
|
|
static inline int msg_done(const struct device *dev, |
|
unsigned int current_msg_flags) |
|
{ |
|
const struct i2c_stm32_config *cfg = dev->config; |
|
I2C_TypeDef *i2c = cfg->i2c; |
|
int64_t start_time = k_uptime_get(); |
|
|
|
/* Wait for transfer to complete */ |
|
while (!LL_I2C_IsActiveFlag_TC(i2c) && !LL_I2C_IsActiveFlag_TCR(i2c)) { |
|
if (check_errors(dev, __func__)) { |
|
return -EIO; |
|
} |
|
if ((k_uptime_get() - start_time) > |
|
I2C_STM32_TRANSFER_TIMEOUT_MSEC) { |
|
return -ETIMEDOUT; |
|
} |
|
} |
|
/* Issue stop condition if necessary */ |
|
if (current_msg_flags & I2C_MSG_STOP) { |
|
LL_I2C_GenerateStopCondition(i2c); |
|
while (!LL_I2C_IsActiveFlag_STOP(i2c)) { |
|
if ((k_uptime_get() - start_time) > |
|
I2C_STM32_TRANSFER_TIMEOUT_MSEC) { |
|
return -ETIMEDOUT; |
|
} |
|
} |
|
|
|
LL_I2C_ClearFlag_STOP(i2c); |
|
LL_I2C_DisableReloadMode(i2c); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int i2c_stm32_msg_write(const struct device *dev, struct i2c_msg *msg, |
|
uint8_t *next_msg_flags, uint16_t slave) |
|
{ |
|
const struct i2c_stm32_config *cfg = dev->config; |
|
I2C_TypeDef *i2c = cfg->i2c; |
|
unsigned int len = 0U; |
|
uint8_t *buf = msg->buf; |
|
int64_t start_time = k_uptime_get(); |
|
|
|
msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_WRITE); |
|
|
|
len = msg->len; |
|
while (len) { |
|
while (1) { |
|
if (LL_I2C_IsActiveFlag_TXIS(i2c)) { |
|
break; |
|
} |
|
|
|
if (check_errors(dev, __func__)) { |
|
return -EIO; |
|
} |
|
|
|
if ((k_uptime_get() - start_time) > |
|
I2C_STM32_TRANSFER_TIMEOUT_MSEC) { |
|
return -ETIMEDOUT; |
|
} |
|
} |
|
|
|
LL_I2C_TransmitData8(i2c, *buf); |
|
buf++; |
|
len--; |
|
} |
|
|
|
return msg_done(dev, msg->flags); |
|
} |
|
|
|
static int i2c_stm32_msg_read(const struct device *dev, struct i2c_msg *msg, |
|
uint8_t *next_msg_flags, uint16_t slave) |
|
{ |
|
const struct i2c_stm32_config *cfg = dev->config; |
|
I2C_TypeDef *i2c = cfg->i2c; |
|
unsigned int len = 0U; |
|
uint8_t *buf = msg->buf; |
|
int64_t start_time = k_uptime_get(); |
|
|
|
msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_READ); |
|
|
|
len = msg->len; |
|
while (len) { |
|
while (!LL_I2C_IsActiveFlag_RXNE(i2c)) { |
|
if (check_errors(dev, __func__)) { |
|
return -EIO; |
|
} |
|
if ((k_uptime_get() - start_time) > |
|
I2C_STM32_TRANSFER_TIMEOUT_MSEC) { |
|
return -ETIMEDOUT; |
|
} |
|
} |
|
|
|
*buf = LL_I2C_ReceiveData8(i2c); |
|
buf++; |
|
len--; |
|
} |
|
|
|
return msg_done(dev, msg->flags); |
|
} |
|
#endif |
|
|
|
#ifdef CONFIG_I2C_STM32_V2_TIMING |
|
/* |
|
* Macro used to fix the compliance check warning : |
|
* "DEEP_INDENTATION: Too many leading tabs - consider code refactoring |
|
* in the i2c_compute_scll_sclh() function below |
|
*/ |
|
#define I2C_LOOP_SCLH(); \ |
|
if ((tscl >= clk_min) && \ |
|
(tscl <= clk_max) && \ |
|
(tscl_h >= i2c_stm32_charac[i2c_speed].hscl_min) && \ |
|
(ti2cclk < tscl_h)) { \ |
|
\ |
|
int32_t error = (int32_t)tscl - (int32_t)ti2cspeed; \ |
|
\ |
|
if (error < 0) { \ |
|
error = -error; \ |
|
} \ |
|
\ |
|
if ((uint32_t)error < prev_error) { \ |
|
prev_error = (uint32_t)error; \ |
|
i2c_valid_timing[count].scll = scll; \ |
|
i2c_valid_timing[count].sclh = sclh; \ |
|
ret = count; \ |
|
} \ |
|
} |
|
|
|
/* |
|
* @brief Calculate SCLL and SCLH and find best configuration. |
|
* @param clock_src_freq I2C source clock in Hz. |
|
* @param i2c_speed I2C frequency (index). |
|
* @retval config index (0 to I2C_VALID_TIMING_NBR], 0xFFFFFFFF for no valid config. |
|
*/ |
|
uint32_t i2c_compute_scll_sclh(uint32_t clock_src_freq, uint32_t i2c_speed) |
|
{ |
|
uint32_t ret = 0xFFFFFFFFU; |
|
uint32_t ti2cclk; |
|
uint32_t ti2cspeed; |
|
uint32_t prev_error; |
|
uint32_t dnf_delay; |
|
uint32_t clk_min, clk_max; |
|
uint32_t scll, sclh; |
|
uint32_t tafdel_min; |
|
|
|
ti2cclk = (NSEC_PER_SEC + (clock_src_freq / 2U)) / clock_src_freq; |
|
ti2cspeed = (NSEC_PER_SEC + (i2c_stm32_charac[i2c_speed].freq / 2U)) / |
|
i2c_stm32_charac[i2c_speed].freq; |
|
|
|
tafdel_min = (I2C_STM32_USE_ANALOG_FILTER == 1U) ? |
|
I2C_STM32_ANALOG_FILTER_DELAY_MIN : |
|
0U; |
|
|
|
/* tDNF = DNF x tI2CCLK */ |
|
dnf_delay = i2c_stm32_charac[i2c_speed].dnf * ti2cclk; |
|
|
|
clk_max = NSEC_PER_SEC / i2c_stm32_charac[i2c_speed].freq_min; |
|
clk_min = NSEC_PER_SEC / i2c_stm32_charac[i2c_speed].freq_max; |
|
|
|
prev_error = ti2cspeed; |
|
|
|
for (uint32_t count = 0; count < I2C_STM32_VALID_TIMING_NBR; count++) { |
|
/* tPRESC = (PRESC+1) x tI2CCLK*/ |
|
uint32_t tpresc = (i2c_valid_timing[count].presc + 1U) * ti2cclk; |
|
|
|
for (scll = 0; scll < I2C_STM32_SCLL_MAX; scll++) { |
|
/* tLOW(min) <= tAF(min) + tDNF + 2 x tI2CCLK + [(SCLL+1) x tPRESC ] */ |
|
uint32_t tscl_l = tafdel_min + dnf_delay + |
|
(2U * ti2cclk) + ((scll + 1U) * tpresc); |
|
|
|
/* |
|
* The I2CCLK period tI2CCLK must respect the following conditions: |
|
* tI2CCLK < (tLOW - tfilters) / 4 and tI2CCLK < tHIGH |
|
*/ |
|
if ((tscl_l > i2c_stm32_charac[i2c_speed].lscl_min) && |
|
(ti2cclk < ((tscl_l - tafdel_min - dnf_delay) / 4U))) { |
|
for (sclh = 0; sclh < I2C_STM32_SCLH_MAX; sclh++) { |
|
/* |
|
* tHIGH(min) <= tAF(min) + tDNF + |
|
* 2 x tI2CCLK + [(SCLH+1) x tPRESC] |
|
*/ |
|
uint32_t tscl_h = tafdel_min + dnf_delay + |
|
(2U * ti2cclk) + ((sclh + 1U) * tpresc); |
|
|
|
/* tSCL = tf + tLOW + tr + tHIGH */ |
|
uint32_t tscl = tscl_l + |
|
tscl_h + i2c_stm32_charac[i2c_speed].trise + |
|
i2c_stm32_charac[i2c_speed].tfall; |
|
|
|
/* get timings with the lowest clock error */ |
|
I2C_LOOP_SCLH(); |
|
} |
|
} |
|
} |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
/* |
|
* Macro used to fix the compliance check warning : |
|
* "DEEP_INDENTATION: Too many leading tabs - consider code refactoring |
|
* in the i2c_compute_presc_scldel_sdadel() function below |
|
*/ |
|
#define I2C_LOOP_SDADEL(); \ |
|
\ |
|
if ((tsdadel >= (uint32_t)tsdadel_min) && \ |
|
(tsdadel <= (uint32_t)tsdadel_max)) { \ |
|
if (presc != prev_presc) { \ |
|
i2c_valid_timing[i2c_valid_timing_nbr].presc = presc; \ |
|
i2c_valid_timing[i2c_valid_timing_nbr].tscldel = scldel; \ |
|
i2c_valid_timing[i2c_valid_timing_nbr].tsdadel = sdadel; \ |
|
prev_presc = presc; \ |
|
i2c_valid_timing_nbr++; \ |
|
\ |
|
if (i2c_valid_timing_nbr >= I2C_STM32_VALID_TIMING_NBR) { \ |
|
break; \ |
|
} \ |
|
} \ |
|
} |
|
|
|
/* |
|
* @brief Compute PRESC, SCLDEL and SDADEL. |
|
* @param clock_src_freq I2C source clock in Hz. |
|
* @param i2c_speed I2C frequency (index). |
|
* @retval None. |
|
*/ |
|
void i2c_compute_presc_scldel_sdadel(uint32_t clock_src_freq, uint32_t i2c_speed) |
|
{ |
|
uint32_t prev_presc = I2C_STM32_PRESC_MAX; |
|
uint32_t ti2cclk; |
|
int32_t tsdadel_min, tsdadel_max; |
|
int32_t tscldel_min; |
|
uint32_t presc, scldel, sdadel; |
|
uint32_t tafdel_min, tafdel_max; |
|
|
|
ti2cclk = (NSEC_PER_SEC + (clock_src_freq / 2U)) / clock_src_freq; |
|
|
|
tafdel_min = (I2C_STM32_USE_ANALOG_FILTER == 1U) ? |
|
I2C_STM32_ANALOG_FILTER_DELAY_MIN : 0U; |
|
tafdel_max = (I2C_STM32_USE_ANALOG_FILTER == 1U) ? |
|
I2C_STM32_ANALOG_FILTER_DELAY_MAX : 0U; |
|
/* |
|
* tDNF = DNF x tI2CCLK |
|
* tPRESC = (PRESC+1) x tI2CCLK |
|
* SDADEL >= {tf +tHD;DAT(min) - tAF(min) - tDNF - [3 x tI2CCLK]} / {tPRESC} |
|
* SDADEL <= {tVD;DAT(max) - tr - tAF(max) - tDNF- [4 x tI2CCLK]} / {tPRESC} |
|
*/ |
|
tsdadel_min = (int32_t)i2c_stm32_charac[i2c_speed].tfall + |
|
(int32_t)i2c_stm32_charac[i2c_speed].hddat_min - |
|
(int32_t)tafdel_min - |
|
(int32_t)(((int32_t)i2c_stm32_charac[i2c_speed].dnf + 3) * |
|
(int32_t)ti2cclk); |
|
|
|
tsdadel_max = (int32_t)i2c_stm32_charac[i2c_speed].vddat_max - |
|
(int32_t)i2c_stm32_charac[i2c_speed].trise - |
|
(int32_t)tafdel_max - |
|
(int32_t)(((int32_t)i2c_stm32_charac[i2c_speed].dnf + 4) * |
|
(int32_t)ti2cclk); |
|
|
|
/* {[tr+ tSU;DAT(min)] / [tPRESC]} - 1 <= SCLDEL */ |
|
tscldel_min = (int32_t)i2c_stm32_charac[i2c_speed].trise + |
|
(int32_t)i2c_stm32_charac[i2c_speed].sudat_min; |
|
|
|
if (tsdadel_min <= 0) { |
|
tsdadel_min = 0; |
|
} |
|
|
|
if (tsdadel_max <= 0) { |
|
tsdadel_max = 0; |
|
} |
|
|
|
for (presc = 0; presc < I2C_STM32_PRESC_MAX; presc++) { |
|
for (scldel = 0; scldel < I2C_STM32_SCLDEL_MAX; scldel++) { |
|
/* TSCLDEL = (SCLDEL+1) * (PRESC+1) * TI2CCLK */ |
|
uint32_t tscldel = (scldel + 1U) * (presc + 1U) * ti2cclk; |
|
|
|
if (tscldel >= (uint32_t)tscldel_min) { |
|
for (sdadel = 0; sdadel < I2C_STM32_SDADEL_MAX; sdadel++) { |
|
/* TSDADEL = SDADEL * (PRESC+1) * TI2CCLK */ |
|
uint32_t tsdadel = (sdadel * (presc + 1U)) * ti2cclk; |
|
|
|
I2C_LOOP_SDADEL(); |
|
} |
|
|
|
if (i2c_valid_timing_nbr >= I2C_STM32_VALID_TIMING_NBR) { |
|
return; |
|
} |
|
} |
|
} |
|
} |
|
} |
|
|
|
int i2c_stm32_configure_timing(const struct device *dev, uint32_t clock) |
|
{ |
|
const struct i2c_stm32_config *cfg = dev->config; |
|
struct i2c_stm32_data *data = dev->data; |
|
I2C_TypeDef *i2c = cfg->i2c; |
|
uint32_t timing = 0U; |
|
uint32_t idx; |
|
uint32_t speed = 0U; |
|
uint32_t i2c_freq = cfg->bitrate; |
|
|
|
/* Reset valid timing count at the beginning of each new computation */ |
|
i2c_valid_timing_nbr = 0; |
|
|
|
if ((clock != 0U) && (i2c_freq != 0U)) { |
|
for (speed = 0 ; speed <= (uint32_t)I2C_STM32_SPEED_FREQ_FAST_PLUS ; speed++) { |
|
if ((i2c_freq >= i2c_stm32_charac[speed].freq_min) && |
|
(i2c_freq <= i2c_stm32_charac[speed].freq_max)) { |
|
i2c_compute_presc_scldel_sdadel(clock, speed); |
|
idx = i2c_compute_scll_sclh(clock, speed); |
|
if (idx < I2C_STM32_VALID_TIMING_NBR) { |
|
timing = ((i2c_valid_timing[idx].presc & |
|
0x0FU) << 28) | |
|
((i2c_valid_timing[idx].tscldel & 0x0FU) << 20) | |
|
((i2c_valid_timing[idx].tsdadel & 0x0FU) << 16) | |
|
((i2c_valid_timing[idx].sclh & 0xFFU) << 8) | |
|
((i2c_valid_timing[idx].scll & 0xFFU) << 0); |
|
} |
|
break; |
|
} |
|
} |
|
} |
|
|
|
/* Fill the current timing value in data structure at runtime */ |
|
data->current_timing.periph_clock = clock; |
|
data->current_timing.i2c_speed = i2c_freq; |
|
data->current_timing.timing_setting = timing; |
|
|
|
LL_I2C_SetTiming(i2c, timing); |
|
|
|
return 0; |
|
} |
|
#else/* CONFIG_I2C_STM32_V2_TIMING */ |
|
|
|
int i2c_stm32_configure_timing(const struct device *dev, uint32_t clock) |
|
{ |
|
const struct i2c_stm32_config *cfg = dev->config; |
|
struct i2c_stm32_data *data = dev->data; |
|
I2C_TypeDef *i2c = cfg->i2c; |
|
uint32_t i2c_hold_time_min, i2c_setup_time_min; |
|
uint32_t i2c_h_min_time, i2c_l_min_time; |
|
uint32_t presc = 1U; |
|
uint32_t timing = 0U; |
|
|
|
/* Look for an adequate preset timing value */ |
|
for (uint32_t i = 0; i < cfg->n_timings; i++) { |
|
const struct i2c_config_timing *preset = &cfg->timings[i]; |
|
uint32_t speed = i2c_map_dt_bitrate(preset->i2c_speed); |
|
|
|
if ((I2C_SPEED_GET(speed) == I2C_SPEED_GET(data->dev_config)) |
|
&& (preset->periph_clock == clock)) { |
|
/* Found a matching periph clock and i2c speed */ |
|
LL_I2C_SetTiming(i2c, preset->timing_setting); |
|
return 0; |
|
} |
|
} |
|
|
|
/* No preset timing was provided, let's dynamically configure */ |
|
switch (I2C_SPEED_GET(data->dev_config)) { |
|
case I2C_SPEED_STANDARD: |
|
i2c_h_min_time = 4000U; |
|
i2c_l_min_time = 4700U; |
|
i2c_hold_time_min = 500U; |
|
i2c_setup_time_min = 1250U; |
|
break; |
|
case I2C_SPEED_FAST: |
|
i2c_h_min_time = 600U; |
|
i2c_l_min_time = 1300U; |
|
i2c_hold_time_min = 375U; |
|
i2c_setup_time_min = 500U; |
|
break; |
|
default: |
|
LOG_ERR("i2c: speed above \"fast\" requires manual timing configuration, " |
|
"see \"timings\" property of st,stm32-i2c-v2 devicetree binding"); |
|
return -EINVAL; |
|
} |
|
|
|
/* Calculate period until prescaler matches */ |
|
do { |
|
uint32_t t_presc = clock / presc; |
|
uint32_t ns_presc = NSEC_PER_SEC / t_presc; |
|
uint32_t sclh = i2c_h_min_time / ns_presc; |
|
uint32_t scll = i2c_l_min_time / ns_presc; |
|
uint32_t sdadel = i2c_hold_time_min / ns_presc; |
|
uint32_t scldel = i2c_setup_time_min / ns_presc; |
|
|
|
if ((sclh - 1) > 255 || (scll - 1) > 255) { |
|
++presc; |
|
continue; |
|
} |
|
|
|
if (sdadel > 15 || (scldel - 1) > 15) { |
|
++presc; |
|
continue; |
|
} |
|
|
|
timing = __LL_I2C_CONVERT_TIMINGS(presc - 1, |
|
scldel - 1, sdadel, sclh - 1, scll - 1); |
|
break; |
|
} while (presc < 16); |
|
|
|
if (presc >= 16U) { |
|
LOG_ERR("I2C:failed to find prescaler value"); |
|
return -EINVAL; |
|
} |
|
|
|
LOG_DBG("I2C TIMING = 0x%x", timing); |
|
LL_I2C_SetTiming(i2c, timing); |
|
|
|
return 0; |
|
} |
|
#endif /* CONFIG_I2C_STM32_V2_TIMING */ |
|
|
|
int i2c_stm32_transaction(const struct device *dev, |
|
struct i2c_msg msg, uint8_t *next_msg_flags, |
|
uint16_t periph) |
|
{ |
|
/* |
|
* Perform a I2C transaction, while taking into account the STM32 I2C V2 |
|
* peripheral has a limited maximum chunk size. Take appropriate action |
|
* if the message to send exceeds that limit. |
|
* |
|
* The last chunk of a transmission uses this function's next_msg_flags |
|
* parameter for its backend calls (_write/_read). Any previous chunks |
|
* use a copy of the current message's flags, with the STOP and RESTART |
|
* bits turned off. This will cause the backend to use reload-mode, |
|
* which will make the combination of all chunks to look like one big |
|
* transaction on the wire. |
|
*/ |
|
const uint32_t i2c_stm32_maxchunk = 255U; |
|
const uint8_t saved_flags = msg.flags; |
|
uint8_t combine_flags = |
|
saved_flags & ~(I2C_MSG_STOP | I2C_MSG_RESTART); |
|
uint8_t *flagsp = NULL; |
|
uint32_t rest = msg.len; |
|
int ret = 0; |
|
|
|
do { /* do ... while to allow zero-length transactions */ |
|
if (msg.len > i2c_stm32_maxchunk) { |
|
msg.len = i2c_stm32_maxchunk; |
|
msg.flags &= ~I2C_MSG_STOP; |
|
flagsp = &combine_flags; |
|
} else { |
|
msg.flags = saved_flags; |
|
flagsp = next_msg_flags; |
|
} |
|
if ((msg.flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) { |
|
ret = i2c_stm32_msg_write(dev, &msg, flagsp, periph); |
|
} else { |
|
ret = i2c_stm32_msg_read(dev, &msg, flagsp, periph); |
|
} |
|
if (ret < 0) { |
|
break; |
|
} |
|
rest -= msg.len; |
|
msg.buf += msg.len; |
|
msg.len = rest; |
|
} while (rest > 0U); |
|
|
|
#ifndef CONFIG_I2C_STM32_INTERRUPT |
|
struct i2c_stm32_data *data = dev->data; |
|
const struct i2c_stm32_config *cfg = dev->config; |
|
I2C_TypeDef *i2c = cfg->i2c; |
|
|
|
if (ret == -ETIMEDOUT) { |
|
if (LL_I2C_IsEnabledReloadMode(i2c)) { |
|
LL_I2C_DisableReloadMode(i2c); |
|
} |
|
#if defined(CONFIG_I2C_TARGET) |
|
data->master_active = false; |
|
if (!data->slave_attached && !data->smbalert_active) { |
|
LL_I2C_Disable(i2c); |
|
} |
|
#else |
|
if (!data->smbalert_active) { |
|
LL_I2C_Disable(i2c); |
|
} |
|
#endif |
|
return -EIO; |
|
} |
|
#endif /* !CONFIG_I2C_STM32_INTERRUPT */ |
|
|
|
return ret; |
|
}
|
|
|