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104 lines
3.8 KiB
104 lines
3.8 KiB
/* |
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* Copyright (c) 2020 Linaro Ltd. |
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* Copyright (c) 2021 Gerson Fernando Budke |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/** @file |
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* @brief Atmel SAM0 MCU family devicetree helper macros |
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*/ |
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#ifndef _ATMEL_SAM0_DT_H_ |
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#define _ATMEL_SAM0_DT_H_ |
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/* Helper macro to get MCLK register address for corresponding |
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* that has corresponding clock enable bit. |
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*/ |
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#define MCLK_MASK_DT_INT_REG_ADDR(n) \ |
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(DT_REG_ADDR(DT_INST_PHANDLE_BY_NAME(n, clocks, mclk)) + \ |
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DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, offset)) |
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/* Helper macros for use with ATMEL SAM0 DMAC controller |
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* return 0xff as default value if there is no 'dmas' property |
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*/ |
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#define ATMEL_SAM0_DT_INST_DMA_CELL(n, name, cell) \ |
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COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \ |
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(DT_INST_DMAS_CELL_BY_NAME(n, name, cell)), \ |
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(0xff)) |
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#define ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, name) \ |
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ATMEL_SAM0_DT_INST_DMA_CELL(n, name, trigsrc) |
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#define ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, name) \ |
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ATMEL_SAM0_DT_INST_DMA_CELL(n, name, channel) |
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#define ATMEL_SAM0_DT_INST_DMA_CTLR(n, name) \ |
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COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \ |
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(DT_INST_DMAS_CTLR_BY_NAME(n, name)), \ |
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(DT_INVALID_NODE)) |
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/* Use to check if a sercom 'n' is enabled for a given 'compat' */ |
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#define ATMEL_SAM0_DT_SERCOM_CHECK(n, compat) \ |
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(sercom##n), compat, okay) |
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/* Use to check if TCC 'n' is enabled for a given 'compat' */ |
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#define ATMEL_SAM0_DT_TCC_CHECK(n, compat) \ |
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(tcc##n), compat, okay) |
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/* Common macro for use to set HCLK_FREQ_HZ */ |
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#define ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ \ |
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DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) |
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/* Devicetree related macros to construct pin mux config data */ |
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/* Get PIN associated with pinctrl-0 pin at index 'i' */ |
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#define ATMEL_SAM0_PIN(node_id, i) \ |
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DT_PHA(DT_PINCTRL_0(node_id, i), atmel_pins, pin) |
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/* Get PIO register address associated with pinctrl-0 pin at index 'i' */ |
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#define ATMEL_SAM0_PIN_TO_PORT_REG_ADDR(node_id, i) \ |
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DT_REG_ADDR(DT_PHANDLE(DT_PINCTRL_0(node_id, i), atmel_pins)) |
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/* Get peripheral cfg associated wiith pinctrl-0 pin at index 'i' */ |
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#define ATMEL_SAM0_PIN_PERIPH(node_id, i) \ |
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DT_PHA(DT_PINCTRL_0(node_id, i), atmel_pins, peripheral) |
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/* Helper function for ATMEL_SAM_PIN_FLAGS */ |
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#define ATMEL_SAM0_PIN_FLAG(node_id, i, flag) \ |
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DT_PROP(DT_PINCTRL_0(node_id, i), flag) |
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/* Convert DT flags to SoC flags */ |
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#define ATMEL_SAM0_PIN_FLAGS(node_id, i) \ |
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(ATMEL_SAM0_PIN_FLAG(node_id, i, bias_pull_up) << SOC_PORT_PULLUP_POS | \ |
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ATMEL_SAM0_PIN_FLAG(node_id, i, bias_pull_down) << SOC_PORT_PULLUP_POS | \ |
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ATMEL_SAM0_PIN_FLAG(node_id, i, input_enable) << SOC_PORT_INPUT_ENABLE_POS | \ |
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ATMEL_SAM0_PIN_FLAG(node_id, i, output_enable) << SOC_PORT_OUTPUT_ENABLE_POS | \ |
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ATMEL_SAM0_PIN_FLAG(node_id, i, pinmux_enable) << SOC_PORT_PMUXEN_ENABLE_POS) |
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/* Construct a soc_port_pin element for pin cfg */ |
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#define ATMEL_SAM0_DT_PORT(node_id, idx) \ |
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{ \ |
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(PortGroup *)ATMEL_SAM0_PIN_TO_PORT_REG_ADDR(node_id, idx), \ |
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ATMEL_SAM0_PIN(node_id, idx), \ |
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ATMEL_SAM0_PIN_PERIPH(node_id, idx) << SOC_PORT_FUNC_POS | \ |
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ATMEL_SAM0_PIN_FLAGS(node_id, idx) \ |
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} |
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/* Get the number of pins for pinctrl-0 */ |
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#define ATMEL_SAM0_DT_NUM_PINS(node_id) DT_NUM_PINCTRLS_BY_IDX(node_id, 0) |
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#define ATMEL_SAM0_DT_INST_NUM_PINS(inst) \ |
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ATMEL_SAM0_DT_NUM_PINS(DT_DRV_INST(inst)) |
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/* internal macro to structure things for use with UTIL_LISTIFY */ |
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#define ATMEL_SAM0_DT_PIN_ELEM(idx, node_id) ATMEL_SAM0_DT_PORT(node_id, idx) |
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/* Construct an array intializer for soc_port_pin for a device instance */ |
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#define ATMEL_SAM0_DT_PINS(node_id) \ |
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{ LISTIFY(ATMEL_SAM0_DT_NUM_PINS(node_id), \ |
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ATMEL_SAM0_DT_PIN_ELEM, (,), node_id) \ |
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} |
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#define ATMEL_SAM0_DT_INST_PINS(inst) \ |
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ATMEL_SAM0_DT_PINS(DT_DRV_INST(inst)) |
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#endif /* _ATMEL_SAM0_SOC_DT_H_ */
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