Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.
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/*
* Copyright (c) 2025 Texas Instruments
* Copyright (c) 2025 Linumiz
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <ti/mspm0/g/mspm0g3507.dtsi>
#include <ti/mspm0/g/mspm0g1x0x_g3x0x-pinctrl.dtsi>
#include <zephyr/dt-bindings/clock/mspm0_clock.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
/ {
model = "TI LP_MSPM0G3507/MSPM0G3507";
compatible = "ti,mspm0g3507";
aliases {
led0 = &led0;
pwm-led0 = &pwm_led0;
};
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,code-partition = &slot0_partition;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpiob 22 GPIO_ACTIVE_HIGH>;
label = "Blue LED";
};
};
pwm_leds {
compatible = "pwm-leds";
pwm_led0: pwm_led0 {
pwms = <&pwma0 0 PWM_MSEC(100) PWM_POLARITY_NORMAL>;
};
};
};
&cpu0 {
clock-frequency = <DT_FREQ_M(80)>;
};
&ulpclk {
clock-frequency = <DT_FREQ_M(40)>;
clk-div = <2>;
};
&mclk {
clock-frequency = <DT_FREQ_M(80)>;
clocks = <&hsclk 0>;
};
&hsclk {
clocks = <&syspll2x 0>;
status = "okay";
};
&syspll2x {
status = "okay";
};
&flash0 {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x8000>;
};
slot0_partition: partition@8000 {
label = "image-0";
reg = <0x00008000 0xC000>;
};
slot1_partition: partition@14000 {
label = "image-1";
reg = <0x00014000 0xC000>;
};
};
};
&pinctrl {
status = "okay";
};
&gpioa {
status = "okay";
};
&gpiob {
status = "okay";
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_tx_pa10 &uart0_rx_pa11>;
pinctrl-names = "default";
};
&pwma0 {
status = "okay";
pinctrl-0 = <&tima0_ccp0_pa0>;
pinctrl-names = "default";
ti,cc-index = <0>;
ti,pwm-mode = "EDGE_ALIGN";
ti,period = <1000>;
};