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125 lines
3.4 KiB
125 lines
3.4 KiB
/* |
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* Copyright (c) 2019-2020 Cobham Gaisler AB |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/* |
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* This is a driver for the GRLIB IRQMP interrupt controller common in LEON |
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* systems. |
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* |
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* Interrupt level 1..15 are SPARC interrupts. Interrupt level 16..31, if |
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* implemented in the interrupt controller, are IRQMP "extended interrupts". |
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* |
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* For more information about IRQMP, see the GRLIB IP Core User's Manual. |
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*/ |
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#define DT_DRV_COMPAT gaisler_irqmp |
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#include <kernel.h> |
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#include <init.h> |
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/* |
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* Register description for IRQMP and IRQAMP interrupt controllers |
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* IRQMP - Multiprocessor Interrupt Controller |
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* IRQ(A)MP - Multiprocessor Interrupt Controller with extended ASMP support |
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*/ |
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#define IRQMP_NCPU_MAX 16 |
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struct irqmp_regs { |
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uint32_t ilevel; /* 0x00 */ |
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uint32_t ipend; /* 0x04 */ |
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uint32_t iforce0; /* 0x08 */ |
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uint32_t iclear; /* 0x0c */ |
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uint32_t mpstat; /* 0x10 */ |
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uint32_t brdlst; /* 0x14 */ |
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uint32_t errstat; /* 0x18 */ |
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uint32_t wdogctrl; /* 0x1c */ |
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uint32_t asmpctrl; /* 0x20 */ |
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uint32_t icselr[2]; /* 0x24 */ |
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uint32_t reserved2c; /* 0x2c */ |
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uint32_t reserved30; /* 0x30 */ |
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uint32_t reserved34; /* 0x34 */ |
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uint32_t reserved38; /* 0x38 */ |
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uint32_t reserved3c; /* 0x3c */ |
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uint32_t pimask[IRQMP_NCPU_MAX]; /* 0x40 */ |
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uint32_t piforce[IRQMP_NCPU_MAX]; /* 0x80 */ |
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uint32_t pextack[IRQMP_NCPU_MAX]; /* 0xc0 */ |
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}; |
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#define IRQMP_PEXTACK_EID (0x1f << 0) |
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static volatile struct irqmp_regs *get_irqmp_regs(void) |
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{ |
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return (struct irqmp_regs *) DT_INST_REG_ADDR(0); |
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} |
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static int get_irqmp_eirq(void) |
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{ |
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return DT_INST_PROP(0, eirq); |
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} |
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void arch_irq_enable(unsigned int source) |
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{ |
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volatile struct irqmp_regs *regs = get_irqmp_regs(); |
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volatile uint32_t *pimask = ®s->pimask[0]; |
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const uint32_t setbit = (1U << source); |
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unsigned int key; |
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key = arch_irq_lock(); |
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*pimask |= setbit; |
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arch_irq_unlock(key); |
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} |
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void arch_irq_disable(unsigned int source) |
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{ |
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volatile struct irqmp_regs *regs = get_irqmp_regs(); |
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volatile uint32_t *pimask = ®s->pimask[0]; |
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const uint32_t keepbits = ~(1U << source); |
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unsigned int key; |
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key = arch_irq_lock(); |
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*pimask &= keepbits; |
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arch_irq_unlock(key); |
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} |
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int arch_irq_is_enabled(unsigned int source) |
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{ |
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volatile struct irqmp_regs *regs = get_irqmp_regs(); |
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volatile uint32_t *pimask = ®s->pimask[0]; |
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return !!(*pimask & (1U << source)); |
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} |
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int z_sparc_int_get_source(int irl) |
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{ |
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volatile struct irqmp_regs *regs = get_irqmp_regs(); |
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const int eirq = get_irqmp_eirq(); |
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int source; |
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if ((eirq != 0) && (irl == eirq)) { |
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source = regs->pextack[0] & IRQMP_PEXTACK_EID; |
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if (source == 0) { |
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source = irl; |
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} |
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} else { |
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source = irl; |
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} |
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return source; |
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} |
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static int irqmp_init(const struct device *dev) |
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{ |
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ARG_UNUSED(dev); |
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volatile struct irqmp_regs *regs = get_irqmp_regs(); |
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regs->ilevel = 0; |
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regs->ipend = 0; |
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regs->iforce0 = 0; |
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regs->pimask[0] = 0; |
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regs->piforce[0] = 0xfffe0000; |
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return 0; |
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} |
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SYS_INIT(irqmp_init, PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY);
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