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88 lines
3.0 KiB
88 lines
3.0 KiB
/* |
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* Copyright (c) 2024 Jianxiong Gu <jianxiong.gu@outlook.com> |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#ifndef ZEPHYR_DRIVERS_USBC_TCPC_RT1715_H_ |
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#define ZEPHYR_DRIVERS_USBC_TCPC_RT1715_H_ |
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#define RT1715_REG_SYS_CTRL_1 0x90 |
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/** VCONN OVP occurs and discharge path turn-on */ |
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#define RT1715_REG_SYS_CTRL_1_VCONN_DISCHARGE_EN BIT(5) |
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/** Low power mode Rd or Rp */ |
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#define RT1715_REG_SYS_CTRL_1_BMCIO_LPR_PRD BIT(4) |
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/** Low power mode enable */ |
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#define RT1715_REG_SYS_CTRL_1_BMCIO_LP_EN BIT(3) |
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/** BMCIO BandGap enable */ |
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#define RT1715_REG_SYS_CTRL_1_BMCIO_BG_EN BIT(2) |
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/** VBUS detection enable */ |
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#define RT1715_REG_SYS_CTRL_1_VBUS_DETECT_EN BIT(1) |
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/** 24M oscillator for BMC communication */ |
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#define RT1715_REG_SYS_CTRL_1_BMCIO_OSC_EN BIT(0) |
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#define RT1715_REG_OCP 0x93 |
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/** VCONN over-current control selection */ |
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#define RT1715_REG_OCP_BMCIO_VCON_OCP GENMASK(7, 5) |
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#define RT1715_VCON_OCP_200MA (0 << 5) |
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#define RT1715_VCON_OCP_300MA (1 << 5) |
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#define RT1715_VCON_OCP_400MA (2 << 5) |
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#define RT1715_VCON_OCP_500MA (3 << 5) |
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#define RT1715_VCON_OCP_600MA (4 << 5) |
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#define RT1715_REG_RT_ST 0x97 |
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/** If VBUS under 0.8V */ |
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#define RT1715_REG_RT_ST_VBUS_80 BIT(1) |
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#define RT1715_REG_RT_INT 0x98 |
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/** Ra detach */ |
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#define RT1715_REG_RT_INT_RA_DETACH BIT(5) |
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/** VBUS under 0.8V */ |
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#define RT1715_REG_RT_INT_VBUS_80 BIT(1) |
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/** Low power mode exited */ |
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#define RT1715_REG_RT_INT_WAKEUP BIT(0) |
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#define RT1715_REG_RT_INT_MASK 0x99 |
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#define RT1715_REG_LP_CTRL 0x9B |
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/** Clock_300K divided from Clock_24M */ |
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#define RT1715_REG_LP_CTRL_CK_300K_SEL BIT(7) |
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/** Non-Shutdown mode */ |
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#define RT1715_REG_LP_CTRL_SHUTDOWN_OFF BIT(5) |
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/** Enable PD3.0 Extended message */ |
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#define RT1715_REG_LP_CTRL_ENEXTMSG BIT(4) |
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/** Auto enter idle mode enable */ |
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#define RT1715_REG_LP_CTRL_AUTOIDLE_EN BIT(3) |
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/** Enter idle mode timeout time */ |
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#define RT1715_REG_LP_CTRL_AUTOIDLE_TIMEOUT GENMASK(2, 0) |
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#define RT1715_AUTOIDLE_TIMEOUT_96P0_MS 7 |
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#define RT1715_AUTOIDLE_TIMEOUT_83P2_MS 6 |
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#define RT1715_AUTOIDLE_TIMEOUT_70P4_MS 5 |
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#define RT1715_AUTOIDLE_TIMEOUT_57P6_MS 4 |
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#define RT1715_AUTOIDLE_TIMEOUT_44P8_MS 3 |
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#define RT1715_AUTOIDLE_TIMEOUT_32P0_MS 2 |
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#define RT1715_AUTOIDLE_TIMEOUT_19P2_MS 1 |
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#define RT1715_AUTOIDLE_TIMEOUT_6P4_MS 0 |
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#define RT1715_REG_SYS_WAKEUP 0x9F |
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/** Wakeup function enable */ |
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#define RT1715_REG_SYS_WAKEUP_EN BIT(7) |
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#define RT1715_REG_SW_RST 0xA0 |
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/** Write 1 to trigger software reset */ |
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#define RT1715_REG_SW_RST_EN BIT(0) |
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#define RT1715_REG_DRP_CTRL_1 0xA2 |
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/** |
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* The period a DRP will complete a Source to Sink and back advertisement. |
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* (Period = TDRP * 6.4 + 51.2ms) |
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*/ |
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#define RT1715_REG_DRP_CTRL_1_TDRP GENMASK(3, 0) |
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#define RT1715_REG_DRP_CTRL_2 0xA3 |
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/** |
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* The percent of time that a DRP will advertise Source during tDRP. |
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* (DUTY = (DCSRCDRP[9:0] + 1) / 1024) |
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*/ |
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#define RT1715_REG_DRP_CTRL_2_DCSRCDRP GENMASK(9, 0) |
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#endif /* ZEPHYR_DRIVERS_USBC_TCPC_UCPD_NUMAKER_H_ */
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