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89 lines
2.6 KiB
89 lines
2.6 KiB
/* |
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* Copyright (c) 2023 Carlo Caione <ccaione@baylibre.com> |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#ifndef ZEPHYR_INCLUDE_SYS_BARRIER_H_ |
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#define ZEPHYR_INCLUDE_SYS_BARRIER_H_ |
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#include <zephyr/toolchain.h> |
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#if defined(CONFIG_BARRIER_OPERATIONS_ARCH) |
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# if defined(CONFIG_ARM) |
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# include <zephyr/arch/arm/barrier.h> |
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# elif defined(CONFIG_ARM64) |
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# include <zephyr/arch/arm64/barrier.h> |
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# endif |
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#elif defined(CONFIG_BARRIER_OPERATIONS_BUILTIN) |
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#include <zephyr/sys/barrier_builtin.h> |
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#endif |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/** |
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* @addtogroup barrier_apis Barrier Services APIs |
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* @ingroup kernel_apis |
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* @{ |
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*/ |
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/** |
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* @brief Full/sequentially-consistent data memory barrier. |
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* |
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* This routine acts as a synchronization fence between threads and prevents |
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* re-ordering of data accesses instructions across the barrier instruction. |
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*/ |
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static ALWAYS_INLINE void barrier_dmem_fence_full(void) |
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{ |
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#if defined(CONFIG_BARRIER_OPERATIONS_ARCH) || defined(CONFIG_BARRIER_OPERATIONS_BUILTIN) |
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z_barrier_dmem_fence_full(); |
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#endif |
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} |
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/** |
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* @brief Full/sequentially-consistent data synchronization barrier. |
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* |
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* This routine acts as a synchronization fence between threads and prevents |
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* re-ordering of data accesses instructions across the barrier instruction |
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* like @ref barrier_dmem_fence_full(), but has the additional effect of |
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* blocking execution of any further instructions, not just loads or stores, or |
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* both, until synchronization is complete. |
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* |
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* @note When not supported by hardware or architecture, this instruction falls |
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* back to a full/sequentially-consistent data memory barrier. |
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*/ |
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static ALWAYS_INLINE void barrier_dsync_fence_full(void) |
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{ |
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#if defined(CONFIG_BARRIER_OPERATIONS_ARCH) || defined(CONFIG_BARRIER_OPERATIONS_BUILTIN) |
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z_barrier_dsync_fence_full(); |
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#endif |
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} |
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/** |
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* @brief Full/sequentially-consistent instruction synchronization barrier. |
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* |
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* This routine is used to guarantee that any subsequent instructions are |
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* fetched and to ensure any previously executed context-changing operations, |
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* such as writes to system control registers, have completed by the time the |
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* routine completes. In hardware terms, this might mean that the instruction |
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* pipeline is flushed, for example. |
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* |
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* @note When not supported by hardware or architecture, this instruction falls |
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* back to a compiler barrier. |
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*/ |
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static ALWAYS_INLINE void barrier_isync_fence_full(void) |
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{ |
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#if defined(CONFIG_BARRIER_OPERATIONS_ARCH) || defined(CONFIG_BARRIER_OPERATIONS_BUILTIN) |
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z_barrier_isync_fence_full(); |
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#endif |
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} |
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/** @} */ |
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#ifdef __cplusplus |
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} /* extern "C" */ |
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#endif |
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#endif /* ZEPHYR_INCLUDE_SYS_ATOMIC_H_ */
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