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135 lines
2.0 KiB
135 lines
2.0 KiB
/* |
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* Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com> |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/dts-v1/; |
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#include <renesas/ra/ra4/r7fa4m1ab3cfm.dtsi> |
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#include "arduino_uno_r4-pinctrl.dtsi" |
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#include <zephyr/dt-bindings/gpio/gpio.h> |
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#include <zephyr/dt-bindings/adc/adc.h> |
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/ { |
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model = "Arduino Uno R4 Board"; |
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compatible = "renesas,ra4m1", "renesas,ra"; |
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chosen { |
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zephyr,console = &uart2; |
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zephyr,shell-uart = &uart2; |
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zephyr,sram = &sram0; |
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zephyr,flash = &flash0; |
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zephyr,entropy = &trng; |
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zephyr,code-partition = &code_partition; |
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}; |
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}; |
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&sci2 { |
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status = "okay"; |
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pinctrl-0 = <&sci2_default>; |
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pinctrl-names = "default"; |
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interrupts = <0 1>, <1 1>, <2 1>, <3 1>; |
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interrupt-names = "rxi", "txi", "tei", "eri"; |
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uart2: uart { |
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current-speed = <115200>; |
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status = "okay"; |
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}; |
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}; |
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&ioport1 { |
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status = "okay"; |
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}; |
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&adc0 { |
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status = "okay"; |
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pinctrl-0 = <&adc0_default>; |
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pinctrl-names = "default"; |
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}; |
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&port_irq0 { |
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interrupts = <27 12>; |
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status = "okay"; |
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}; |
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&port_irq1 { |
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interrupts = <28 12>; |
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status = "okay"; |
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}; |
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&trng { |
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status = "okay"; |
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}; |
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&pwm7 { |
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pinctrl-0 = <&pwm7_default>; |
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pinctrl-names = "default"; |
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interrupts = <8 1>, <9 1>; |
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interrupt-names = "gtioca", "overflow"; |
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status = "okay"; |
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}; |
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&iic1 { |
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pinctrl-0 = <&iic1_default>; |
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pinctrl-names = "default"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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clock-frequency = <DT_FREQ_M(1)>; |
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interrupts = <10 1>, <11 1>, <12 1>, <13 1>; |
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interrupt-names = "rxi", "txi", "tei", "eri"; |
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status = "okay"; |
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}; |
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&flash0 { |
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partitions { |
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compatible = "fixed-partitions"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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boot_partition: partition@0 { |
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label = "bootloader"; |
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reg = <0x00000000 0x4000>; |
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read-only; |
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}; |
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code_partition: partition@4000 { |
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label = "code"; |
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reg = <0x4000 0x3C000>; |
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read-only; |
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}; |
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}; |
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}; |
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&hoco { |
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status = "okay"; |
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clock-frequency = <48000000>; |
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}; |
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&pclkblock { |
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clocks = <&hoco>; |
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}; |
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&iclk { |
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div = <1>; |
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}; |
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&pclka { |
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div = <1>; |
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}; |
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&pclkb { |
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div = <2>; |
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}; |
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&pclkc { |
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div = <1>; |
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}; |
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&pclkd { |
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div = <1>; |
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}; |
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&fclk { |
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div = <2>; |
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};
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