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128 lines
4.1 KiB
128 lines
4.1 KiB
/* |
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* Copyright (c) 2024-2025 Renesas Electronics Corporation |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <string.h> |
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#include <zephyr/drivers/clock_control.h> |
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#include <zephyr/kernel.h> |
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#include <soc.h> |
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#include <zephyr/dt-bindings/clock/ra_clock.h> |
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#include <zephyr/drivers/clock_control/renesas_ra_cgc.h> |
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pclkblock)) |
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#define MSTP_REGS_ELEM(node_id, prop, idx) \ |
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[DT_STRING_TOKEN_BY_IDX(node_id, prop, idx)] = \ |
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(volatile uint32_t *)DT_REG_ADDR_BY_IDX(node_id, idx), |
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static volatile uint32_t *mstp_regs[] = { |
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DT_FOREACH_PROP_ELEM(DT_NODELABEL(pclkblock), reg_names, MSTP_REGS_ELEM)}; |
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#else |
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static volatile uint32_t *mstp_regs[] = {}; |
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#endif |
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#if defined(CONFIG_CORTEX_M_SYSTICK) |
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/* If a CPU clock exists in the system, it will be the source for the CPU */ |
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#if BSP_FEATURE_CGC_HAS_CPUCLK |
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(cpu0)) |
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#define sys_clk DT_NODELABEL(cpuclk0) |
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#elif DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(cpu1)) |
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#define sys_clk DT_NODELABEL(cpuclk1) |
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#else |
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#define sys_clk DT_NODELABEL(cpuclk) |
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#endif |
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#else |
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#define sys_clk DT_NODELABEL(iclk) |
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#endif |
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#define SYS_CLOCK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / DT_PROP(sys_clk, div)) |
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BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == SYS_CLOCK_HZ, |
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"CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC must match the configuration of the clock " |
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"supplying the CPU "); |
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#endif |
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static int clock_control_renesas_ra_on(const struct device *dev, clock_control_subsys_t sys) |
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{ |
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struct clock_control_ra_subsys_cfg *subsys_clk = (struct clock_control_ra_subsys_cfg *)sys; |
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if (!dev || !sys) { |
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return -EINVAL; |
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} |
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WRITE_BIT(*mstp_regs[subsys_clk->mstp], subsys_clk->stop_bit, false); |
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return 0; |
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} |
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static int clock_control_renesas_ra_off(const struct device *dev, clock_control_subsys_t sys) |
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{ |
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struct clock_control_ra_subsys_cfg *subsys_clk = (struct clock_control_ra_subsys_cfg *)sys; |
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if (!dev || !sys) { |
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return -EINVAL; |
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} |
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WRITE_BIT(*mstp_regs[subsys_clk->mstp], subsys_clk->stop_bit, true); |
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return 0; |
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} |
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static int clock_control_renesas_ra_get_rate(const struct device *dev, clock_control_subsys_t sys, |
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uint32_t *rate) |
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{ |
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const struct clock_control_ra_pclk_cfg *config = dev->config; |
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uint32_t clk_src_rate; |
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uint32_t clk_div_val; |
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if (!dev || !sys || !rate) { |
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return -EINVAL; |
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} |
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clk_src_rate = R_BSP_SourceClockHzGet(config->clk_src); |
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clk_div_val = config->clk_div; |
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*rate = clk_src_rate / clk_div_val; |
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return 0; |
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} |
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/** |
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* @brief Initializes a peripheral clock device driver |
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*/ |
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static int clock_control_ra_init_pclk(const struct device *dev) |
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{ |
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ARG_UNUSED(dev); |
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return 0; |
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} |
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static int clock_control_ra_init(const struct device *dev) |
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{ |
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ARG_UNUSED(dev); |
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/* Call to HAL layer to initialize system clock and peripheral clock */ |
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bsp_clock_init(); |
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return 0; |
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} |
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static DEVICE_API(clock_control, clock_control_reneas_ra_api) = { |
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.on = clock_control_renesas_ra_on, |
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.off = clock_control_renesas_ra_off, |
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.get_rate = clock_control_renesas_ra_get_rate, |
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}; |
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#define INIT_PCLK(node_id) \ |
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IF_ENABLED(DT_NODE_HAS_COMPAT(node_id, renesas_ra_cgc_pclk), \ |
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(static const struct clock_control_ra_pclk_cfg node_id##_cfg = \ |
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{.clk_src = COND_CODE_1( \ |
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DT_NODE_HAS_PROP(node_id, clocks), \ |
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(RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(node_id))), \ |
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(RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_PARENT(node_id))))), \ |
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.clk_div = DT_PROP(node_id, div)}; \ |
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DEVICE_DT_DEFINE(node_id, &clock_control_ra_init_pclk, NULL, NULL, \ |
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&node_id##_cfg, PRE_KERNEL_1, \ |
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CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, \ |
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&clock_control_reneas_ra_api))); |
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DEVICE_DT_DEFINE(DT_NODELABEL(pclkblock), &clock_control_ra_init, NULL, NULL, NULL, PRE_KERNEL_1, |
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CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, NULL); |
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DT_FOREACH_CHILD_STATUS_OKAY(DT_NODELABEL(pclkblock), INIT_PCLK);
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