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51 lines
1.0 KiB
51 lines
1.0 KiB
/* |
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* Copyright (c) 2023 Google LLC. |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/dts-v1/; |
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#include <mem.h> |
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#include <xtensa/xtensa.dtsi> |
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/ { |
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model = "nxp_adsp_rt595"; |
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compatible = "nxp"; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "cdns,tensilica-xtensa-lx6"; |
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reg = <0>; |
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}; |
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}; |
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sram0: memory@0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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device_type = "memory"; |
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compatible = "mmio-sram"; |
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/* Reserve first 512kB of shared memory for ADSP. */ |
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reg = <0x0 DT_SIZE_K(512)>; |
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/* Reset section must always be at 0 and at least 1kB. */ |
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adsp_reset: memory@0 { |
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reg = <0x0 DT_SIZE_K(1)>; |
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}; |
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/* Code and data sections can be moved around and resized if needed. */ |
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adsp_text: memory@400 { |
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reg = <0x400 DT_SIZE_K(255)>; |
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}; |
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/* On RT595 ADSP shared RAM is mapped at offset 0 on the code bus and at |
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* offset 0x800000 on the data bus. |
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*/ |
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adsp_data: memory@840000 { |
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reg = <0x840000 DT_SIZE_K(256)>; |
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}; |
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}; |
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chosen { |
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zephyr,sram = &adsp_data; |
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}; |
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};
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