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377 lines
9.7 KiB
377 lines
9.7 KiB
/* |
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* Copyright 2022-2023 NXP |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <zephyr/init.h> |
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#include "fsl_power.h" |
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#include <zephyr/pm/policy.h> |
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#include "board.h" |
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#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP |
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#include "flash_clock_setup.h" |
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#endif |
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/* OTP fuse index. */ |
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#define FRO_192MHZ_SC_TRIM 0x2C |
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#define FRO_192MHZ_RD_TRIM 0x2B |
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#define FRO_96MHZ_SC_TRIM 0x2E |
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#define FRO_96MHZ_RD_TRIM 0x2D |
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#define OTP_FUSE_READ_API ((void (*)(uint32_t addr, uint32_t *data))0x1300805D) |
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#define PMIC_MODE_BOOT 0U |
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#define PMIC_MODE_DEEP_SLEEP 1U |
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#define PMIC_MODE_FRO192M_900MV 2U |
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#define PMIC_MODE_FRO96M_800MV 3U |
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#define PMIC_SETTLING_TIME 2000U /* in micro-seconds */ |
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static uint32_t sc_trim_192, rd_trim_192, sc_trim_96, rd_trim_96; |
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#if CONFIG_REGULATOR |
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#include <zephyr/drivers/regulator.h> |
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#define NODE_PCA9420 DT_NODELABEL(pca9420) |
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#define NODE_SW1 DT_NODELABEL(pca9420_sw1) |
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#define NODE_SW2 DT_NODELABEL(pca9420_sw2) |
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#define NODE_LDO1 DT_NODELABEL(pca9420_ldo1) |
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#define NODE_LDO2 DT_NODELABEL(pca9420_ldo2) |
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static const struct device *pca9420 = DEVICE_DT_GET(NODE_PCA9420); |
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static const struct device *sw1 = DEVICE_DT_GET(NODE_SW1); |
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static const struct device *sw2 = DEVICE_DT_GET(NODE_SW2); |
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static const struct device *ldo1 = DEVICE_DT_GET(NODE_LDO1); |
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static const struct device *ldo2 = DEVICE_DT_GET(NODE_LDO2); |
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static int current_power_profile; |
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#define MEGA (1000000U) |
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/* Core frequency levels number. */ |
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#define POWER_FREQ_LEVELS_NUM (5U) |
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/* Invalid voltage level. */ |
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#define POWER_INVALID_VOLT_LEVEL (0xFFFFFFFFU) |
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static const uint32_t power_freq_level[POWER_FREQ_LEVELS_NUM] = { |
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275U * MEGA, |
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230U * MEGA, |
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192U * MEGA, |
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100U * MEGA, |
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60U * MEGA |
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}; |
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/* System clock frequency. */ |
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extern uint32_t SystemCoreClock; |
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static const int32_t sw1_volt[] = {1100000, 1000000, 900000, 800000, 700000}; |
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static int32_t board_calc_volt_level(void) |
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{ |
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uint32_t i; |
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uint32_t volt; |
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for (i = 0U; i < POWER_FREQ_LEVELS_NUM; i++) { |
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if (SystemCoreClock > power_freq_level[i]) { |
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break; |
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} |
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} |
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/* Frequency exceed max supported */ |
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if (i == 0U) { |
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volt = POWER_INVALID_VOLT_LEVEL; |
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} else { |
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volt = sw1_volt[i - 1U]; |
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} |
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return volt; |
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} |
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static int board_config_pmic(void) |
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{ |
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uint32_t volt; |
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int ret = 0; |
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volt = board_calc_volt_level(); |
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ret = regulator_set_voltage(sw1, volt, volt); |
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if (ret != 0) { |
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return ret; |
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} |
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ret = regulator_set_voltage(sw2, 1800000, 1800000); |
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if (ret != 0) { |
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return ret; |
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} |
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ret = regulator_set_voltage(ldo1, 1800000, 1800000); |
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if (ret != 0) { |
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return ret; |
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} |
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ret = regulator_set_voltage(ldo2, 3300000, 3300000); |
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if (ret != 0) { |
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return ret; |
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} |
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/* We can enter deep low power modes */ |
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pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES); |
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return ret; |
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} |
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static int board_pmic_change_mode(uint8_t pmic_mode) |
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{ |
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int ret; |
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if (pmic_mode >= 4) { |
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return -ERANGE; |
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} |
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ret = regulator_parent_dvs_state_set(pca9420, pmic_mode); |
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if (ret != -EPERM) { |
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return ret; |
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} |
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POWER_SetPmicMode(pmic_mode, kCfg_Run); |
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k_busy_wait(PMIC_SETTLING_TIME); |
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return 0; |
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} |
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/* Changes power-related config to preset profiles, like clocks and VDDCORE voltage */ |
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__ramfunc int32_t power_manager_set_profile(uint32_t power_profile) |
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{ |
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bool voltage_changed = false; |
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int32_t current_uv, future_uv; |
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int ret; |
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if (power_profile == current_power_profile) { |
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return 0; |
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} |
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/* Confirm valid power_profile, and read the new VDDCORE voltage */ |
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switch (power_profile) { |
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case POWER_PROFILE_AFTER_BOOT: |
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future_uv = DT_PROP(NODE_SW1, nxp_mode0_microvolt); |
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break; |
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case POWER_PROFILE_FRO192M_900MV: |
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future_uv = DT_PROP(NODE_SW1, nxp_mode2_microvolt); |
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break; |
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case POWER_PROFILE_FRO96M_800MV: |
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future_uv = DT_PROP(NODE_SW1, nxp_mode3_microvolt); |
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break; |
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default: |
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return -EINVAL; |
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} |
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if (current_power_profile == POWER_PROFILE_AFTER_BOOT) { |
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/* One-Time optimization after boot */ |
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POWER_DisableLVD(); |
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CLOCK_AttachClk(kFRO_DIV1_to_MAIN_CLK); |
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/* Set SYSCPUAHBCLKDIV divider to value 1 */ |
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CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1U); |
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/* Other clock optimizations */ |
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#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP |
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flexspi_setup_clock(FLEXSPI0, 0U, 1U); /* main_clk div by 1 */ |
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#endif |
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/* Disable the PFDs of SYSPLL */ |
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CLKCTL0->SYSPLL0PFD |= CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE_MASK | |
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CLKCTL0_SYSPLL0PFD_PFD1_CLKGATE_MASK | |
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CLKCTL0_SYSPLL0PFD_PFD2_CLKGATE_MASK; |
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POWER_EnablePD(kPDRUNCFG_PD_SYSPLL_LDO); |
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POWER_EnablePD(kPDRUNCFG_PD_SYSPLL_ANA); |
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POWER_EnablePD(kPDRUNCFG_PD_AUDPLL_LDO); |
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POWER_EnablePD(kPDRUNCFG_PD_AUDPLL_ANA); |
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POWER_EnablePD(kPDRUNCFG_PD_SYSXTAL); |
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/* Configure MCU that PMIC supplies will be powered in all |
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* PMIC modes |
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*/ |
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PMC->PMICCFG = 0xFF; |
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} |
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/* Get current and future PMIC voltages to determine DVFS sequence */ |
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ret = regulator_get_voltage(sw1, ¤t_uv); |
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if (ret) { |
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return ret; |
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} |
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if (power_profile == POWER_PROFILE_FRO192M_900MV) { |
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/* check if voltage or frequency change is first */ |
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if (future_uv > current_uv) { |
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/* Increase voltage first before frequencies */ |
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ret = board_pmic_change_mode(PMIC_MODE_FRO192M_900MV); |
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if (ret) { |
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return ret; |
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} |
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voltage_changed = true; |
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} |
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/* Trim FRO to 192MHz */ |
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CLKCTL0->FRO_SCTRIM = sc_trim_192; |
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CLKCTL0->FRO_RDTRIM = rd_trim_192; |
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/* Reset the EXP_COUNT. */ |
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CLKCTL0->FRO_CONTROL &= ~CLKCTL0_FRO_CONTROL_EXP_COUNT_MASK; |
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CLOCK_AttachClk(kFRO_DIV1_to_MAIN_CLK); |
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/* Set SYSCPUAHBCLKDIV divider to value 1 */ |
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CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1U); |
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if (voltage_changed == false) { |
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ret = board_pmic_change_mode(PMIC_MODE_FRO192M_900MV); |
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if (ret) { |
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return ret; |
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} |
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} |
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} else if (power_profile == POWER_PROFILE_FRO96M_800MV) { |
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/* This PMIC mode is the lowest voltage used for DVFS, |
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* Reduce frequency first, and then reduce voltage |
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*/ |
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/* Trim the FRO to 96MHz */ |
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CLKCTL0->FRO_SCTRIM = sc_trim_96; |
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CLKCTL0->FRO_RDTRIM = rd_trim_96; |
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/* Reset the EXP_COUNT. */ |
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CLKCTL0->FRO_CONTROL &= ~CLKCTL0_FRO_CONTROL_EXP_COUNT_MASK; |
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CLOCK_AttachClk(kFRO_DIV1_to_MAIN_CLK); |
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/* Set SYSCPUAHBCLKDIV divider to value 1 */ |
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CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1U); |
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ret = board_pmic_change_mode(PMIC_MODE_FRO96M_800MV); |
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if (ret) { |
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return ret; |
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} |
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} |
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current_power_profile = power_profile; |
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return 0; |
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} |
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#endif /* CONFIG_REGULATOR */ |
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static int mimxrt595_evk_init(void) |
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{ |
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/* Set the correct voltage range according to the board. */ |
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power_pad_vrange_t vrange = { |
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.Vdde0Range = kPadVol_171_198, |
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.Vdde1Range = kPadVol_171_198, |
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.Vdde2Range = kPadVol_171_198, |
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.Vdde3Range = kPadVol_300_360, |
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.Vdde4Range = kPadVol_171_198 |
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}; |
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POWER_SetPadVolRange(&vrange); |
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/* Do not enter deep low power modes until the PMIC modes have been initialized */ |
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pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES); |
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#ifdef CONFIG_I2S |
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/* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm3 */ |
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SYSCTL1->SHAREDCTRLSET[0] = SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL(3) | |
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SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL(3); |
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#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES |
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/* Select Data in from Transmit I2S - Flexcomm 3 */ |
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SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL(3); |
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/* Enable Transmit I2S - Flexcomm 3 for Shared Data Out */ |
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SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN(1); |
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#endif |
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/* Set Receive I2S - Flexcomm 1 SCK, WS from shared signal set 0 */ |
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SYSCTL1->FCCTRLSEL[1] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) | |
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SYSCTL1_FCCTRLSEL_WSINSEL(1); |
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/* Set Transmit I2S - Flexcomm 3 SCK, WS from shared signal set 0 */ |
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SYSCTL1->FCCTRLSEL[3] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) | |
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SYSCTL1_FCCTRLSEL_WSINSEL(1); |
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#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES |
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/* Select Receive I2S - Flexcomm 1 Data in from shared signal set 0 */ |
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SYSCTL1->FCCTRLSEL[1] |= SYSCTL1_FCCTRLSEL_DATAINSEL(1); |
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/* Select Transmit I2S - Flexcomm 3 Data out to shared signal set 0 */ |
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SYSCTL1->FCCTRLSEL[3] |= SYSCTL1_FCCTRLSEL_DATAOUTSEL(1); |
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#endif |
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#endif |
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#ifdef CONFIG_REBOOT |
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/* |
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* The sys_reboot API calls NVIC_SystemReset. On the RT595, the warm |
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* reset will not complete correctly unless the ROM toggles the |
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* flash reset pin. We can control this behavior using the OTP shadow |
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* register for OPT word BOOT_CFG1 |
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* |
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* Set FLEXSPI_RESET_PIN_ENABLE=1, FLEXSPI_RESET_PIN= PIO4_5 |
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*/ |
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OCOTP0->OTP_SHADOW[97] = 0x164000; |
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#endif /* CONFIG_REBOOT */ |
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/* Read 192M FRO clock Trim settings from fuses. |
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* NOTE: Reading OTP fuses requires a VDDCORE voltage of at least 1.0V |
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*/ |
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OTP_FUSE_READ_API(FRO_192MHZ_SC_TRIM, &sc_trim_192); |
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OTP_FUSE_READ_API(FRO_192MHZ_RD_TRIM, &rd_trim_192); |
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/* Read 96M FRO clock Trim settings from fuses. */ |
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OTP_FUSE_READ_API(FRO_96MHZ_SC_TRIM, &sc_trim_96); |
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OTP_FUSE_READ_API(FRO_96MHZ_RD_TRIM, &rd_trim_96); |
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/* Check if the 96MHz fuses have been programmed. |
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* Production devices have 96M trim values programmed in OTP fuses. |
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* However, older EVKs may have pre-production silicon. |
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*/ |
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if ((rd_trim_96 == 0) && (sc_trim_96 == 0)) { |
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/* If not programmed then use software to calculate the trim values */ |
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CLOCK_FroTuneToFreq(96000000u); |
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rd_trim_96 = CLKCTL0->FRO_RDTRIM; |
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sc_trim_96 = sc_trim_192; |
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} |
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return 0; |
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} |
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#ifdef CONFIG_LV_Z_VBD_CUSTOM_SECTION |
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extern char __flexspi2_start[]; |
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extern char __flexspi2_end[]; |
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static int init_psram_framebufs(void) |
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{ |
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/* |
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* Framebuffers will be stored in PSRAM, within FlexSPI2 linker |
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* section. Zero out BSS section. |
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*/ |
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memset(__flexspi2_start, 0, __flexspi2_end - __flexspi2_start); |
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return 0; |
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} |
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#endif /* CONFIG_LV_Z_VBD_CUSTOM_SECTION */ |
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#if CONFIG_REGULATOR |
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/* PMIC setup is dependent on the regulator API */ |
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SYS_INIT(board_config_pmic, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY); |
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#endif |
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#ifdef CONFIG_LV_Z_VBD_CUSTOM_SECTION |
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/* Framebuffers should be setup after PSRAM is initialized but before |
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* Graphics framework init |
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*/ |
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SYS_INIT(init_psram_framebufs, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY); |
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#endif |
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SYS_INIT(mimxrt595_evk_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);
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