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70 lines
2.7 KiB
70 lines
2.7 KiB
/* |
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* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#pragma once |
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/* LP-SRAM (16kB) memory */ |
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#define LPSRAM_IRAM_START DT_REG_ADDR(DT_NODELABEL(sramlp)) |
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#define LPSRAM_SIZE DT_REG_SIZE(DT_NODELABEL(sramlp)) |
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#define ULP_SHARED_MEM DT_REG_SIZE(DT_NODELABEL(shmlp)) |
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#define ULP_COPROC_RESERVE_MEM (0x4000) |
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/* HP-SRAM (512kB) memory */ |
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#define HPSRAM_START DT_REG_ADDR(DT_NODELABEL(sramhp)) |
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#define HPSRAM_SIZE DT_REG_SIZE(DT_NODELABEL(sramhp)) |
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#define HPSRAM_DRAM_START HPSRAM_START |
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#define HPSRAM_IRAM_START HPSRAM_START |
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/* ICache size is fixed to 32KB on ESP32-C6 */ |
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#define ICACHE_SIZE 0x8000 |
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/** Simplified memory map for the bootloader. |
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* Make sure the bootloader can load into main memory without overwriting itself. |
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* |
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* ESP32-C6 ROM static data usage is as follows: |
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* - 0x4086ad08 - 0x4087c610: Shared buffers, used in UART/USB/SPI download mode only |
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* - 0x4087c610 - 0x4087e610: PRO CPU stack, can be reclaimed as heap after RTOS startup |
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* - 0x4087e610 - 0x40880000: ROM .bss and .data (not easily reclaimable) |
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* |
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* The 2nd stage bootloader can take space up to the end of ROM shared |
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* buffers area (0x4087c610). |
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*/ |
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#define DRAM_BUFFERS_START 0x4086ad08 |
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#define DRAM_BUFFERS_END 0x4087c610 |
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#define DRAM_STACK_START DRAM_BUFFERS_END |
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#define DRAM_ROM_BSS_DATA_START 0x4087e610 |
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/* Set the limit for the application runtime dynamic allocations */ |
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#define DRAM_RESERVED_START DRAM_BUFFERS_END |
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/* For safety margin between bootloader data section and startup stacks */ |
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#define BOOTLOADER_STACK_OVERHEAD 0x0 |
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/* These lengths can be adjusted, if necessary: FIXME: optimize ram usage */ |
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#define BOOTLOADER_DRAM_SEG_LEN 0xA000 |
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#define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x3000 |
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#define BOOTLOADER_IRAM_SEG_LEN 0xC000 |
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/* Base address used for calculating memory layout |
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* counted from Dbus backwards and back to the Ibus |
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*/ |
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#define BOOTLOADER_USER_SRAM_END (DRAM_BUFFERS_START - BOOTLOADER_STACK_OVERHEAD) |
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/* Start of the lower region is determined by region size and the end of the higher region */ |
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#define BOOTLOADER_IRAM_LOADER_SEG_START (BOOTLOADER_USER_SRAM_END - BOOTLOADER_IRAM_LOADER_SEG_LEN) |
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#define BOOTLOADER_IRAM_SEG_START (BOOTLOADER_IRAM_LOADER_SEG_START - BOOTLOADER_IRAM_SEG_LEN) |
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#define BOOTLOADER_DRAM_SEG_START (BOOTLOADER_IRAM_SEG_START - BOOTLOADER_DRAM_SEG_LEN) |
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/* Flash */ |
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#ifdef CONFIG_FLASH_SIZE |
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#define FLASH_SIZE CONFIG_FLASH_SIZE |
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#else |
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#define FLASH_SIZE 0x400000 |
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#endif |
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/* Cached memory */ |
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#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE |
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#define IROM_SEG_ORG 0x42000000 |
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#define IROM_SEG_LEN FLASH_SIZE |
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#define DROM_SEG_ORG 0x42800000 |
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#define DROM_SEG_LEN FLASH_SIZE
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