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255 lines
7.4 KiB
255 lines
7.4 KiB
/* |
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* Copyright (c) 2025 Renesas Electronics Corporation |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RZA2M_CPG_LLD_H_ |
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#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RZA2M_CPG_LLD_H_ |
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#include <stdint.h> |
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#include <zephyr/dt-bindings/clock/renesas_rza2m_clock.h> |
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struct rza2m_cpg_clock_config { |
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DEVICE_MMIO_ROM; |
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uint32_t cpg_extal_freq_hz_cfg; |
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uint32_t cpg_iclk_freq_hz_cfg; |
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uint32_t cpg_bclk_freq_hz_cfg; |
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uint32_t cpg_p1clk_freq_hz_cfg; |
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}; |
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struct rza2m_cpg_clock_data { |
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DEVICE_MMIO_RAM; |
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uint32_t cpg_extal_frequency_hz; |
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uint32_t cpg_pll_frequency_hz; |
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uint32_t cpg_iclk_divisor; |
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uint32_t cpg_iclk_frequency_hz; |
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uint32_t cpg_bclk_divisor; |
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uint32_t cpg_bclk_frequency_hz; |
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uint32_t cpg_p1clk_divisor; |
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uint32_t cpg_p1clk_frequency_hz; |
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}; |
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#define PL310_BASE_ADDR 0x1F003000UL |
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#define PL310_PWR_CTRL_OFFSET 0xF80UL |
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#define PL310_PWR_CTRL_STANDBY_MODE_EN_SHIFT 0UL |
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#define STBACK_REG_WAIT_US 50 |
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#define RZA2M_CPG_KHZ(khz) ((khz) * 1000U) |
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#define RZA2M_CPG_MHZ(mhz) (RZA2M_CPG_KHZ(mhz) * 1000U) |
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#define CPG_BASE_ADDR DEVICE_MMIO_GET(dev) |
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#define CPG_FRQCR_OFFSET 0x0UL |
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#define CPG_CKIOSEL_OFFSET 0xF0UL |
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#define CPG_SCLKSEL_OFFSET 0xF4UL |
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#define CPG_REG_ADDR(off) ((mm_reg_t)(CPG_BASE_ADDR + (off))) |
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#define RZA2M_GET_MODULE(clock_id) ((clock_id >> RZA2M_MODULE_SHIFT) & 0xFF) |
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#define RZA2M_GET_CLOCK_SRC(clock_id) ((clock_id >> RZA2M_CLOCK_SRC_SHIFT) & 0xFF) |
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#define STBCR1_OFFSET 0x10UL |
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#define STBCR2_OFFSET 0x14UL |
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#define STBCR3_OFFSET 0x410UL |
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#define STBCR4_OFFSET 0x414UL |
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#define STBCR5_OFFSET 0x418UL |
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#define STBCR6_OFFSET 0x41CUL |
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#define STBCR7_OFFSET 0x420UL |
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#define STBCR8_OFFSET 0x424UL |
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#define STBCR9_OFFSET 0x428UL |
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#define STBCR10_OFFSET 0x42CUL |
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#define STBREQ1_OFFSET 0x20UL |
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#define STBREQ2_OFFSET 0x24UL |
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#define STBREQ3_OFFSET 0x28UL |
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#define STBACK1_OFFSET 0x30UL |
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#define STBACK2_OFFSET 0x34UL |
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#define STBACK3_OFFSET 0x38UL |
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#define CPG_FRQCR_PFC 0x0003UL |
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#define CPG_FRQCR_PFC_SHIFT 0UL |
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#define CPG_FRQCR_BFC 0x0030UL |
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#define CPG_FRQCR_BFC_SHIFT 4UL |
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#define CPG_FRQCR_IFC 0x0300UL |
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#define CPG_FRQCR_IFC_SHIFT 8UL |
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#define CPG_FRQCR_CKOEN 0x3000UL |
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#define CPG_FRQCR_CKOEN_SHIFT 12UL |
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#define CPG_FRQCR_CKOEN2 0x4000UL |
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#define CPG_FRQCR_CKOEN2_SHIFT 14UL |
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#define CPG_STBCR2_MSTP20 0x01UL |
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#define CPG_STBREQ1_STBRQ10 0x01UL |
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#define CPG_STBREQ1_STBRQ11 0x02UL |
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#define CPG_STBREQ1_STBRQ12 0x04UL |
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#define CPG_STBREQ1_STBRQ13 0x08UL |
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#define CPG_STBREQ1_STBRQ15 0x20UL |
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#define CPG_STBREQ2_STBRQ20 0x01UL |
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#define CPG_STBREQ2_STBRQ21 0x02UL |
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#define CPG_STBREQ2_STBRQ22 0x04UL |
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#define CPG_STBREQ2_STBRQ23 0x08UL |
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#define CPG_STBREQ2_STBRQ24 0x10UL |
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#define CPG_STBREQ2_STBRQ25 0x20UL |
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#define CPG_STBREQ2_STBRQ26 0x40UL |
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#define CPG_STBREQ2_STBRQ27 0x80UL |
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#define CPG_STBREQ3_STBRQ30 0x01UL |
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#define CPG_STBREQ3_STBRQ31 0x02UL |
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#define CPG_STBREQ3_STBRQ32 0x04UL |
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#define CPG_STBREQ3_STBRQ33 0x08UL |
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#define CPG_STBACK1_STBAK10 0x01UL |
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#define CPG_STBACK1_STBAK11 0x02UL |
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#define CPG_STBACK1_STBAK12 0x04UL |
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#define CPG_STBACK1_STBAK13 0x08UL |
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#define CPG_STBACK1_STBAK15 0x20UL |
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#define CPG_STBACK2_STBAK20 0x01UL |
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#define CPG_STBACK2_STBAK21 0x02UL |
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#define CPG_STBACK2_STBAK22 0x04UL |
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#define CPG_STBACK2_STBAK23 0x08UL |
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#define CPG_STBACK2_STBAK24 0x10UL |
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#define CPG_STBACK2_STBAK25 0x20UL |
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#define CPG_STBACK2_STBAK26 0x40UL |
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#define CPG_STBACK2_STBAK27 0x80UL |
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#define CPG_STBACK3_STBAK30 0x01UL |
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#define CPG_STBACK3_STBAK31 0x02UL |
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#define CPG_STBACK3_STBAK32 0x04UL |
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#define CPG_STBACK3_STBAK33 0x08UL |
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#define CPG_CKIOSEL_CKIOSEL 0x0003UL |
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#define CPG_SCLKSEL_SPICR 0x0003UL |
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#define CPG_SCLKSEL_HYMCR 0x0030UL |
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#define CPG_SCLKSEL_OCTCR 0x0300UL |
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#define CPG_STBCR3_MSTP30 0x01UL |
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#define CPG_STBCR3_MSTP32 0x04UL |
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#define CPG_STBCR3_MSTP33 0x08UL |
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#define CPG_STBCR3_MSTP34 0x10UL |
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#define CPG_STBCR3_MSTP35 0x20UL |
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#define CPG_STBCR3_MSTP36 0x40UL |
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#define CPG_STBCR4_MSTP40 0x01UL |
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#define CPG_STBCR4_MSTP41 0x02UL |
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#define CPG_STBCR4_MSTP42 0x04UL |
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#define CPG_STBCR4_MSTP43 0x08UL |
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#define CPG_STBCR4_MSTP44 0x10UL |
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#define CPG_STBCR4_MSTP45 0x20UL |
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#define CPG_STBCR4_MSTP46 0x40UL |
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#define CPG_STBCR4_MSTP47 0x80UL |
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#define CPG_STBCR5_MSTP51 0x02UL |
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#define CPG_STBCR5_MSTP52 0x04UL |
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#define CPG_STBCR5_MSTP53 0x08UL |
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#define CPG_STBCR5_MSTP56 0x40UL |
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#define CPG_STBCR5_MSTP57 0x80UL |
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#define CPG_STBCR6_MSTP60 0x01UL |
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#define CPG_STBCR6_MSTP61 0x02UL |
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#define CPG_STBCR6_MSTP62 0x04UL |
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#define CPG_STBCR6_MSTP63 0x08UL |
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#define CPG_STBCR6_MSTP64 0x10UL |
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#define CPG_STBCR6_MSTP65 0x20UL |
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#define CPG_STBCR6_MSTP66 0x40UL |
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#define CPG_STBCR7_MSTP70 0x01UL |
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#define CPG_STBCR7_MSTP71 0x02UL |
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#define CPG_STBCR7_MSTP72 0x04UL |
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#define CPG_STBCR7_MSTP73 0x08UL |
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#define CPG_STBCR7_MSTP75 0x20UL |
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#define CPG_STBCR7_MSTP76 0x40UL |
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#define CPG_STBCR7_MSTP77 0x80UL |
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#define CPG_STBCR8_MSTP81 0x02UL |
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#define CPG_STBCR8_MSTP83 0x08UL |
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#define CPG_STBCR8_MSTP84 0x10UL |
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#define CPG_STBCR8_MSTP85 0x20UL |
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#define CPG_STBCR8_MSTP86 0x40UL |
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#define CPG_STBCR8_MSTP87 0x80UL |
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#define CPG_STBCR9_MSTP90 0x01UL |
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#define CPG_STBCR9_MSTP91 0x02UL |
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#define CPG_STBCR9_MSTP92 0x04UL |
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#define CPG_STBCR9_MSTP93 0x08UL |
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#define CPG_STBCR9_MSTP95 0x20UL |
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#define CPG_STBCR9_MSTP96 0x40UL |
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#define CPG_STBCR9_MSTP97 0x80UL |
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#define CPG_STBCR10_MSTP100 0x01UL |
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#define CPG_STBCR10_MSTP101 0x02UL |
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#define CPG_STBCR10_MSTP102 0x04UL |
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#define CPG_STBCR10_MSTP103 0x08UL |
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#define CPG_STBCR10_MSTP104 0x10UL |
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#define CPG_STBCR10_MSTP107 0x80UL |
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enum rza2m_stb_module { |
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MODULE_CORESIGHT = 1, |
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MODULE_OSTM0, |
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MODULE_OSTM1, |
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MODULE_OSTM2, |
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MODULE_MTU3, |
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MODULE_CANFD, |
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MODULE_ADC, |
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MODULE_GPT, |
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MODULE_SCIFA0, |
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MODULE_SCIFA1, |
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MODULE_SCIFA2, |
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MODULE_SCIFA3, |
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MODULE_SCIFA4, |
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MODULE_SCI0, |
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MODULE_SCI1, |
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MODULE_IrDA, |
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MODULE_CEU, |
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MODULE_RTC0, |
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MODULE_RTC1, |
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MODULE_JCU, |
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MODULE_VIN, |
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MODULE_ETHER, |
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MODULE_USB0, |
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MODULE_USB1, |
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MODULE_IMR2, |
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MODULE_DRW, |
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MODULE_MIPI, |
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MODULE_SSIF0, |
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MODULE_SSIF1, |
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MODULE_SSIF2, |
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MODULE_SSIF3, |
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MODULE_I2C0, |
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MODULE_I2C1, |
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MODULE_I2C2, |
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MODULE_I2C3, |
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MODULE_SPIBSC, |
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MODULE_VDC6, |
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MODULE_RSPI0, |
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MODULE_RSPI1, |
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MODULE_RSPI2, |
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MODULE_HYPERBUS, |
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MODULE_OCTAMEM, |
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MODULE_RSPDIF, |
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MODULE_DRP, |
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MODULE_TSIP, |
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MODULE_NAND, |
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MODULE_SDMMC0, |
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MODULE_SDMMC1, |
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MODULE_MAX, |
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}; |
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struct rza2m_stb_module_info { |
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enum rza2m_stb_module module; |
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uint32_t reg_offset; |
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uint8_t mask; |
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}; |
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/* For setting any system sub-clock */ |
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enum rza2m_cp_sub_clock { |
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CPG_SUB_CLOCK_ICLK = 0u, /*!< CPU Clock */ |
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CPG_SUB_CLOCK_BCLK, /*!< Internal Bus Clock */ |
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CPG_SUB_CLOCK_P1CLK, /*!< Peripheral Clock */ |
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}; |
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/* For retrieve clock frequency */ |
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enum rza2m_cpg_get_freq_src { |
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CPG_FREQ_EXTAL = 0, |
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CPG_FREQ_ICLK, |
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CPG_FREQ_GCLK, |
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CPG_FREQ_BCLK, |
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CPG_FREQ_P1CLK, |
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CPG_FREQ_P0CLK, |
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}; |
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int rza2m_cpg_set_sub_clock_divider(const struct device *dev, enum rza2m_cp_sub_clock clk_sub_src, |
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uint32_t sub_clk_frequency_hz); |
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int rza2m_cpg_mstp_clock_endisable(const struct device *dev, enum rza2m_stb_module module, |
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bool enable); |
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int rza2m_cpg_get_clock(const struct device *dev, enum rza2m_cpg_get_freq_src src, |
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uint32_t *p_freq); |
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void rza2m_cpg_calculate_pll_frequency(const struct device *dev); |
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void rza2m_pl310_set_standby_mode(void); |
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#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RZA2M_CPG_LLD_H_ */
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