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72 lines
1.8 KiB
72 lines
1.8 KiB
/* |
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com> |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/** |
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* @file |
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* @brief ARM64 Cortex-A interrupt management |
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*/ |
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#include <zephyr/kernel.h> |
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#include <zephyr/arch/cpu.h> |
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#include <zephyr/tracing/tracing.h> |
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#include <zephyr/irq.h> |
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#include <zephyr/toolchain.h> |
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#include <zephyr/linker/sections.h> |
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#include <zephyr/sw_isr_table.h> |
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#include <zephyr/drivers/interrupt_controller/gic.h> |
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void z_arm64_fatal_error(unsigned int reason, z_arch_esf_t *esf); |
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#if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) |
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/* |
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* The default interrupt controller for AArch64 is the ARM Generic Interrupt |
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* Controller (GIC) and therefore the architecture interrupt control functions |
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* are mapped to the GIC driver interface. |
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* |
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* When a custom interrupt controller is used (i.e. |
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* CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER is enabled), the architecture |
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* interrupt control functions are mapped to the SoC layer in |
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* `include/arch/arm64/irq.h`. |
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*/ |
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void arch_irq_enable(unsigned int irq) |
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{ |
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arm_gic_irq_enable(irq); |
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} |
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void arch_irq_disable(unsigned int irq) |
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{ |
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arm_gic_irq_disable(irq); |
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} |
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int arch_irq_is_enabled(unsigned int irq) |
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{ |
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return arm_gic_irq_is_enabled(irq); |
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} |
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void z_arm64_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) |
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{ |
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arm_gic_irq_set_priority(irq, prio, flags); |
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} |
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#endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */ |
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#ifdef CONFIG_DYNAMIC_INTERRUPTS |
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int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, |
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void (*routine)(const void *parameter), |
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const void *parameter, uint32_t flags) |
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{ |
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z_isr_install(irq, routine, parameter); |
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z_arm64_irq_priority_set(irq, priority, flags); |
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return irq; |
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} |
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#endif |
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void z_irq_spurious(const void *unused) |
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{ |
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ARG_UNUSED(unused); |
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z_arm64_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); |
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}
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