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48 lines
1.2 KiB
48 lines
1.2 KiB
/* |
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* Copyright (c) 2018 Intel Corporation |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <zephyr/init.h> |
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#include <zephyr/kernel.h> |
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#include <kernel_arch_data.h> |
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#include <kernel_arch_func.h> |
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#include <zephyr/arch/x86/msr.h> |
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#include <zephyr/arch/x86/cpuid.h> |
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/* |
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* See: |
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* https://software.intel.com/security-software-guidance/api-app/sites/default/files/336996-Speculative-Execution-Side-Channel-Mitigations.pdf |
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*/ |
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#if defined(CONFIG_DISABLE_SSBD) || defined(CONFIG_ENABLE_EXTENDED_IBRS) |
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static int spec_ctrl_init(const struct device *dev) |
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{ |
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ARG_UNUSED(dev); |
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uint32_t enable_bits = 0U; |
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uint32_t cpuid7 = z_x86_cpuid_extended_features(); |
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#ifdef CONFIG_DISABLE_SSBD |
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if ((cpuid7 & CPUID_SPEC_CTRL_SSBD) != 0U) { |
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enable_bits |= X86_SPEC_CTRL_MSR_SSBD; |
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} |
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#endif |
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#ifdef CONFIG_ENABLE_EXTENDED_IBRS |
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if ((cpuid7 & CPUID_SPEC_CTRL_IBRS) != 0U) { |
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enable_bits |= X86_SPEC_CTRL_MSR_IBRS; |
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} |
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#endif |
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if (enable_bits != 0U) { |
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uint64_t cur = z_x86_msr_read(X86_SPEC_CTRL_MSR); |
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z_x86_msr_write(X86_SPEC_CTRL_MSR, |
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cur | enable_bits); |
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} |
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return 0; |
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} |
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SYS_INIT(spec_ctrl_init, PRE_KERNEL_1, 0); |
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#endif /* CONFIG_DISABLE_SSBD || CONFIG_ENABLE_EXTENDED_IBRS */
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