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135 lines
3.8 KiB
135 lines
3.8 KiB
/* |
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* Copyright (c) 2024 BayLibre, SAS |
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* Copyright (c) 2024 Analog Devices Inc. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <stdint.h> |
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#include <errno.h> |
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#include <zephyr/device.h> |
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#include <zephyr/kernel.h> |
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#include <zephyr/drivers/clock_control.h> |
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#include <zephyr/drivers/clock_control/stm32_clock_control.h> |
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#include <zephyr/drivers/pinctrl.h> |
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#include <zephyr/drivers/mdio.h> |
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#include <zephyr/net/ethernet.h> |
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#include <zephyr/net/mdio.h> |
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#include <zephyr/logging/log.h> |
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LOG_MODULE_REGISTER(mdio_stm32_hal, CONFIG_MDIO_LOG_LEVEL); |
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#define DT_DRV_COMPAT st_stm32_mdio |
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#define ADIN1100_REG_VALUE_MASK GENMASK(15, 0) |
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struct mdio_stm32_data { |
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struct k_sem sem; |
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ETH_HandleTypeDef heth; |
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}; |
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struct mdio_stm32_config { |
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const struct pinctrl_dev_config *pincfg; |
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struct stm32_pclken pclken; |
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}; |
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static int mdio_stm32_read(const struct device *dev, uint8_t prtad, |
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uint8_t regad, uint16_t *data) |
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{ |
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struct mdio_stm32_data *const dev_data = dev->data; |
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ETH_HandleTypeDef *heth = &dev_data->heth; |
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uint32_t read; |
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int ret; |
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k_sem_take(&dev_data->sem, K_FOREVER); |
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#ifdef CONFIG_ETH_STM32_HAL_API_V2 |
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ret = HAL_ETH_ReadPHYRegister(heth, prtad, regad, &read); |
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#else |
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heth->Init.PhyAddress = prtad; |
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ret = HAL_ETH_ReadPHYRegister(heth, regad, &read); |
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#endif |
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k_sem_give(&dev_data->sem); |
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if (ret != HAL_OK) { |
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return -EIO; |
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} |
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*data = read & ADIN1100_REG_VALUE_MASK; |
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return ret; |
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} |
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static int mdio_stm32_write(const struct device *dev, uint8_t prtad, |
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uint8_t regad, uint16_t data) |
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{ |
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struct mdio_stm32_data *const dev_data = dev->data; |
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ETH_HandleTypeDef *heth = &dev_data->heth; |
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int ret; |
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k_sem_take(&dev_data->sem, K_FOREVER); |
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#ifdef CONFIG_ETH_STM32_HAL_API_V2 |
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ret = HAL_ETH_WritePHYRegister(heth, prtad, regad, data); |
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#else |
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heth->Init.PhyAddress = prtad; |
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ret = HAL_ETH_WritePHYRegister(heth, regad, data); |
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#endif |
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k_sem_give(&dev_data->sem); |
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if (ret != HAL_OK) { |
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return -EIO; |
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} |
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return ret; |
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} |
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static int mdio_stm32_init(const struct device *dev) |
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{ |
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struct mdio_stm32_data *const dev_data = dev->data; |
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const struct mdio_stm32_config *const config = dev->config; |
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int ret; |
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/* enable clock */ |
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ret = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), |
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(clock_control_subsys_t)&config->pclken); |
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if (ret < 0) { |
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LOG_ERR("Failed to enable ethernet clock needed for MDIO (%d)", ret); |
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return ret; |
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} |
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ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); |
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if (ret < 0) { |
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return ret; |
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} |
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k_sem_init(&dev_data->sem, 1, 1); |
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return 0; |
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} |
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static DEVICE_API(mdio, mdio_stm32_api) = { |
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.read = mdio_stm32_read, |
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.write = mdio_stm32_write, |
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}; |
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#define MDIO_STM32_HAL_DEVICE(inst) \ |
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PINCTRL_DT_INST_DEFINE(inst); \ |
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\ |
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static struct mdio_stm32_data mdio_stm32_data_##inst = { \ |
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.heth = {.Instance = (ETH_TypeDef *)DT_REG_ADDR(DT_INST_PARENT(inst))}, \ |
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}; \ |
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static struct mdio_stm32_config mdio_stm32_config_##inst = { \ |
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.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \ |
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.pclken = {.bus = DT_CLOCKS_CELL_BY_NAME(DT_INST_PARENT(inst), stm_eth, bus), \ |
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.enr = DT_CLOCKS_CELL_BY_NAME(DT_INST_PARENT(inst), stm_eth, bits)}, \ |
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}; \ |
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DEVICE_DT_INST_DEFINE(inst, &mdio_stm32_init, NULL, &mdio_stm32_data_##inst, \ |
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&mdio_stm32_config_##inst, POST_KERNEL, CONFIG_MDIO_INIT_PRIORITY, \ |
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&mdio_stm32_api); |
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DT_INST_FOREACH_STATUS_OKAY(MDIO_STM32_HAL_DEVICE)
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