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359 lines
14 KiB
359 lines
14 KiB
.. _cyclonev_socdk: |
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Intel® Cyclone® V SoC Development Kit |
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##################################### |
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Overview |
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******** |
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The Zephyr kernel is supported on the Intel® Cyclone® V SoC Development Kit, |
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using its Hard Processor System (HPS) CPU. |
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.. figure:: img/cv_soc_board.jpg |
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:align: center |
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:alt: Intel's Cyclone® V SoC FPGA DevKit |
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Intel®'s Cyclone® V SoC FPGA DevKit (Credit: Intel®) |
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Hardware |
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******** |
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Jumpers and DIP Switch settings |
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=============================== |
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Recommended board settings are the same as the GSRD for Cyclone® V |
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SoC Development Board. |
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There are two sets of switches on the back of the board. Of particular |
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importance is SW2. First, the board jumpers need to be configured as follows: |
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* J5 : Open |
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* J6 : Short |
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* J7 : Short |
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* J9 : Open |
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* J13: Short |
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* J16: Open |
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* J26: Short pins 1-2 |
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* J27: Short pins 2-3 |
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* J28: Short pins 1-2 |
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* J29: Short pins 2-3 |
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* J30: Short pins 1-2 |
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* J31: Open |
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Then, the board switches need to be configured as follows: |
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* SW1: All OFF |
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* SW2: All OFF |
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* SW3: ON-OFF-ON-OFF-ON-ON |
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* SW4: OFF-OFF-ON-ON |
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Other switches are user switches, their position is application-specific. |
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Refer to the development kit user manual for specifics about jumpers and switches |
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Necessary Software |
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================== |
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You will need the Intel® Quartus® Prime SDK in order to work with this device. The |
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`Intel® Quartus® Prime Lite Edition <https://www.intel.com/content/www/us/en/software-kit/684215/intel-quartus-prime-lite-edition-design-software-version-21-1-for-linux.html>`_ |
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for Linux may be obtained without charge. |
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For your convenience using the SDK tools (such as ``quartus_pgm``), |
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you should put the binaries provided by the SDK |
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in your path. Below is an example, adjust ALTERA_BASE to where you installed the |
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SDK: |
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.. code-block:: console |
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export QUARTUS_ROOTDIR=/opt/intelFPGA_lite/21.1 |
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export PATH=$PATH:$QUARTUS_ROOTDIR/quartus/bin:$QUARTUS_ROOTDIR/programmer/bin |
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You may need to adjust your udev rules so that you can talk to the USB Blaster |
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II peripheral, which is the built-in JTAG interface for this device. |
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The following works for Ubuntu: |
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.. code-block:: console |
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# For Altera USB-Blaster permissions. |
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SUBSYSTEM=="usb",\ |
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ENV{DEVTYPE}=="usb_device",\ |
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ATTR{idVendor}=="09fb",\ |
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ATTR{idProduct}=="6010",\ |
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MODE="0666",\ |
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NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ |
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RUN+="/bin/chmod 0666 %c" |
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SUBSYSTEM=="usb",\ |
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ENV{DEVTYPE}=="usb_device",\ |
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ATTR{idVendor}=="09fb",\ |
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ATTR{idProduct}=="6810",\ |
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MODE="0666",\ |
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NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ |
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RUN+="/bin/chmod 0666 %c" |
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You can test connectivity with the SDK jtagconfig tool, you should see something |
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like: |
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.. code-block:: console |
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$ jtagconfig |
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1) USB-BlasterII [1-5] |
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4ba00477 SOCVHPS |
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02D020DD 5ZSEBA6(.|ES)/5CSEMA6/.. |
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Golden Reference Design |
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======================= |
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The Golden System Reference Design (GSRD) provides a set of essential hardware |
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and software system componets that can be used as a starting point for various |
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custom user designs. |
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The Zephyr support for Cyclone® V SoC Development Kit is based on GSRD hardware. |
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Please refer to `Intel® Cyclone® V SoC GSRD <https://rocketboards.org/foswiki/Documentation/CycloneVSoCGSRD>`_ |
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The hardware use for this release is based on Intel® Quartus® version 21.1 |
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the hardware files can be found `here <https://releases.rocketboards.org/release/2018.05/gsrd/hw/cv_soc_devkit_ghrd.tar.gz>`_ |
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The directory "cv_soc_devkit_ghrd" contains the necessary files to create |
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a Intel® Quartus® project: |
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* ghrd_top.v : top level Verilog (HDL) file for the GSRD |
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* soc_system.qpf : Quartus® Prime Project File |
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* soc_system.qsf : Quartus® Prime Settings File |
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* soc_system.qsys : Platform Designer file (contains the SoC system) |
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* soc_system.sopcinfo : SOPC Information file contains details about modules instantiated in the project, parameter names and values. |
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* soc_system_timing.sdc : Synopsys Desing Constraint FILE. |
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* output_files/soc_system.sof : FPGA configuration file. |
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Flash this FPGA file (.sof) using the ``quartus_pgm`` SDK tool with the FPGA |
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configuration file soc_system.sof: |
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.. code-block:: console |
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$ quartus_pgm -m jtag -o "p;path/to/soc_system.sof" |
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This system is composed by the HPS, ARM Cortex-A9. In this example the UART, timer, |
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USB, I2C, DDR memory are exposed. Please double check the peripheral you intend to |
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use have its corresponding driver support. |
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You can find more information of the Cyclone® V SoC Devkit GSRD in RocketBoards |
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or consult the "Cyclone® V Hard Processor System Technical Reference Manual" |
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Console Output |
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============== |
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16550 UART |
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---------- |
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By default, the kernel is configured to send console output to the 16550 UART. |
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You can monitor this on your workstation by connecting to the top right mini USB |
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port on the board (J8/UART) (it will show up in /dev as a ttyUSB node), and then running |
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minicom/PuTTy with flow control disabled, 115200-8N1 settings. |
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Programming and Debugging |
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************************* |
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Flashing |
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======== |
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Flashing Kernel into the board |
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------------------------------ |
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The usual ``flash`` target will work with the ``cyclonev_socdk`` board |
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configuration. Here is an example for the :ref:`hello_world` |
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application. |
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``Important!!!`` : Before flashing the board a ``preloader`` is required, |
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you can download `cv_soc_devkit_ghrd.tar.gz <https://releases.rocketboards.org/release/2018.05/gsrd/hw/cv_soc_devkit_ghrd.tar.gz>`_, |
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extract the file and copy ``cv_soc_devkit_ghrd/software/preloader/uboot-socfpga/spl/u-boot-spl`` |
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to :zephyr_file:`boards/intel/socfpga_std/cyclonev_socdk/support/` |
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.. zephyr-app-commands:: |
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:zephyr-app: samples/hello_world |
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:board: cyclonev_socdk |
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:goals: flash |
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Refer to :ref:`build_an_application` and :ref:`application_run` for |
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more details. |
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This provisions the Zephyr kernel and the CPU configuration onto the board, |
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using the customized OpenOCD runner script :zephyr_file:`scripts/west_commands/runners/intel_cyclonev.py` |
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After it completes the kernel will immediately boot using the GSRD preloader. |
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Notice that there a lot of helper files to ``flash`` the application with |
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OpenOCD and GDB Debbuger (Zephyr SDK must be installed in your machine). |
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This files should be located in :zephyr_file:`boards/intel/socfpga_std/cyclonev_socdk/support/` including: |
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* blaster_6810.hex : USB-BlasterII firmware |
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* tmp_preloader_dl_cmd.txt : GDB helper file to load the preloader |
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* tmp_appli_dl_cmd.gdb : GDB helper file to load the zephyr.elf file |
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* tmp_appli_debug_cmd.gdb : GDB helper file to load the zephyr.elf file while debugging |
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* openocd.cfg : sources configuration files for OpenOCD |
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* download_all.gdb : GDB helper file to load the preloader |
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* u-boot-spl : Cyclone® V SoC DevKit GSRD preloader (copied from GSRD: cv_soc_devkit_ghrd.tar.gz) |
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The following image shows the expected output (UART) after executing "west flash" using |
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the "hello world" sample design: |
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.. figure:: img/cyclonev_westflash.jpg |
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:align: center |
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:alt: UART output after "west flash" example |
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UART output after "west flash" example (Credit: Intel®) |
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Debugging |
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========= |
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The Zephyr SDK includes a GDB server which can be used to debug a Cyclone® V |
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SoC Development Kit board. |
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You can either debug a running image that was flashed onto the device in User |
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Flash Memory (UFM), or load an image over the JTAG using GDB. |
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Debugging With Flashed Image |
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---------------------------- |
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You can debug an application in the usual way. Here is an example. |
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.. zephyr-app-commands:: |
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:zephyr-app: samples/hello_world |
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:board: cyclonev_socdk |
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:goals: debug |
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You will see output similar to the following: |
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.. code-block:: console |
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-- west debug: rebuilding |
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ninja: no work to do. |
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-- west debug: using runner intel_cyclonev |
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-- runners.intel_cyclonev: OpenOCD GDB server running on port 3333; no thread info available |
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Open On-Chip Debugger 0.11.0+dev-00244-g7e3dbbbe2 (2021-11-18-07:14) |
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Licensed under GNU GPL v2 |
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For bug reports, read http://openocd.org/doc/doxygen/bugs.html |
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Info : only one transport option; autoselect 'jtag' |
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cycv_dbginit |
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Info : Listening on port 6666 for tcl connections |
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Info : Listening on port 4444 for telnet connections |
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Info : Altera USB-Blaster II (uninitialized) found |
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Info : Loading firmware... |
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Info : Waiting for reenumerate... |
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Info : Waiting for reenumerate... |
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Info : Altera USB-Blaster II found (Firm. rev. = 1.39) |
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Info : This adapter doesn't support configurable speed |
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Info : JTAG tap: fpgasoc.fpga.tap tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0) |
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Info : JTAG tap: fpgasoc.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) |
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Info : DAP transaction stalled (WAIT) - slowing down |
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Info : DAP transaction stalled (WAIT) - slowing down |
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Info : fpgasoc.cpu.0: hardware has 6 breakpoints, 4 watchpoints |
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Info : starting gdb server for fpgasoc.cpu.0 on 3333 |
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Info : Listening on port 3333 for gdb connections |
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Info : accepting 'gdb' connection on tcp/3333 |
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Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 |
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Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT |
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target halted in ARM state due to debug-request, current mode: Supervisor |
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cpsr: 0x600001d3 pc: 0x00002fa4 |
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MMU: disabled, D-Cache: disabled, I-Cache: enabled |
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warning: No executable has been specified and target does not support |
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determining executable automatically. Try using the "file" command. |
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0x00002fa4 in ?? () |
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Restoring section .text (0xffff0000 to 0xffff6f84) |
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Info : DAP transaction stalled (WAIT) - slowing down |
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Warn : keep_alive() was not invoked in the 1000 ms timelimit. GDB alive packet not sent! (1469 ms). Workaround: increase "set remotetimeout" in GDB |
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Restoring section .rodata (0xffff6f84 to 0xffff8af9) |
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Restoring section .data (0xffff8b00 to 0xffff99d4) |
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Info : DAP transaction stalled (WAIT) - slowing down |
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Hardware assisted breakpoint 1 at 0xffff147e |
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Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 |
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fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 |
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Temporary breakpoint 1, 0xffff147e in spl_boot_device () |
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[Inferior 1 (Remote target) detached] |
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Info : dropped 'gdb' connection |
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shutdown command invoked |
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Open On-Chip Debugger 0.11.0+dev-00244-g7e3dbbbe2 (2021-11-18-07:14) |
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Licensed under GNU GPL v2 |
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For bug reports, read http://openocd.org/doc/doxygen/bugs.html |
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Info : only one transport option; autoselect 'jtag' |
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cycv_dbginit |
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Info : Listening on port 6666 for tcl connections |
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Info : Listening on port 4444 for telnet connections |
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Info : Altera USB-Blaster II found (Firm. rev. = 1.39) |
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Info : This adapter doesn't support configurable speed |
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Info : JTAG tap: fpgasoc.fpga.tap tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0) |
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Info : JTAG tap: fpgasoc.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) |
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Info : DAP transaction stalled (WAIT) - slowing down |
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Info : DAP transaction stalled (WAIT) - slowing down |
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Info : fpgasoc.cpu.0: hardware has 6 breakpoints, 4 watchpoints |
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Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 |
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Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT |
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Info : starting gdb server for fpgasoc.cpu.0 on 3333 |
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Info : Listening on port 3333 for gdb connections |
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Info : accepting 'gdb' connection on tcp/3333 |
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warning: No executable has been specified and target does not support |
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determining executable automatically. Try using the "file" command. |
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0xffff147c in ?? () |
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warning: /home/demo/zephyrproject/zephyr/boards/intel/socfpga_std/cyclonev_socdk/support/tmp_appli_debug_cmd.gdb: No such file or directory |
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[Inferior 1 (Remote target) detached] |
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Info : dropped 'gdb' connection |
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shutdown command invoked |
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Open On-Chip Debugger 0.11.0+dev-00244-g7e3dbbbe2 (2021-11-18-07:14) |
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Licensed under GNU GPL v2 |
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For bug reports, read http://openocd.org/doc/doxygen/bugs.html |
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Info : only one transport option; autoselect 'jtag' |
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cycv_dbginit |
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Info : Listening on port 6666 for tcl connections |
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Info : Listening on port 4444 for telnet connections |
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Info : Altera USB-Blaster II found (Firm. rev. = 1.39) |
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Info : This adapter doesn't support configurable speed |
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Info : JTAG tap: fpgasoc.fpga.tap tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0) |
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Info : JTAG tap: fpgasoc.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) |
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Info : DAP transaction stalled (WAIT) - slowing down |
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Info : DAP transaction stalled (WAIT) - slowing down |
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Info : fpgasoc.cpu.0: hardware has 6 breakpoints, 4 watchpoints |
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Reading symbols from /home/demo/zephyrproject/zephyr/build/zephyr/zephyr.elf... |
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Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 |
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Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT |
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Info : starting gdb server for fpgasoc.cpu.0 on 3333 |
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Info : Listening on port 3333 for gdb connections |
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Remote debugging using :3333 |
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Info : accepting 'gdb' connection on tcp/3333 |
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main () at /home/demo/zephyrproject/zephyr/samples/hello_world/src/main.c:11 |
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11 printk("Hello World! %s\n", CONFIG_BOARD); |
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(gdb) |
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Try other examples |
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================== |
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There are varios examples that can be downloaded to the Cyclone® V SoC FPGA |
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Development Kit Board. Try to ``blink`` an LED from the HPS side of the chip: |
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.. zephyr-app-commands:: |
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:zephyr-app: samples/basic/blinky |
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:board: cyclonev_socdk |
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:goals: flash |
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.. figure:: img/cyclonev_blinky.jpg |
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:align: center |
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:alt: HPS LED0 blinking example |
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HPS LED0 blinking example (Credit: Intel®) |
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Try writing characters to the LCD display connected to the i2c bus: |
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.. zephyr-app-commands:: |
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:zephyr-app: samples/drivers/lcd_cyclonev_socdk |
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:board: cyclonev_socdk |
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:goals: flash |
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References |
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********** |
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* `Cyclone® V Hard Processor System Technical Reference Manual <https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_54001.pdf>`_ |
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* `Cyclone® V SoC Development Kit and Intel® SoC FPGA Embedded Development Suite <https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/cyclone/v-sx.html>`_ |
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* `Cyclone® V SoC GSRD in RocketBoards.org <https://rocketboards.org/foswiki/Documentation/CycloneVSoCGSRD>`_ |
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* `Intel® FPGA Software Download Center <https://www.intel.com/content/www/us/en/collections/products/fpga/software/downloads.html>`_ |
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* `Embedded Peripherals IP User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_embedded_ip.pdf>`_ |
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* `Quartus II Scripting Reference Manual <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/tclscriptrefmnl.pdf>`_
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