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91 lines
3.3 KiB
91 lines
3.3 KiB
/* |
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* Copyright (c) 2021 Laird Connectivity |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <zephyr/devicetree.h> |
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#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h> |
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#define REGION_MASK_BASE_ADDRESS 0x00000000U |
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#define REGION_ITCM_BASE_ADDRESS 0x00000000U |
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#define REGION_QSPI_BASE_ADDRESS 0x08000000U |
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#define REGION_DTCM_BASE_ADDRESS 0x20000000U |
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#define REGION_DDR_BASE_ADDRESS 0x40000000U |
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#define REGION_DDR2_BASE_ADDRESS 0x80000000U |
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#if defined(CONFIG_CODE_DDR) |
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#define REGION_DDR_NONCACHE_BASE_ADDRESS 0x80000000U |
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#define REGION_DDR_NONCACHE_SIZE 0x00400000U |
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#endif |
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static const struct arm_mpu_region mpu_regions[] = { |
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/* |
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* Region 0 [0x0000_0000 - 0x4000_0000]: |
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* Memory with Device type, not executable, not shareable, non-cacheable. |
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*/ |
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MPU_REGION_ENTRY("MASK", REGION_MASK_BASE_ADDRESS, |
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{ ARM_MPU_RASR(1, ARM_MPU_AP_FULL, |
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0, 0, 0, 1, 0, ARM_MPU_REGION_SIZE_1GB) }), |
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/* |
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* Region 1 ITCM[0x0000_0000 - 0x0001_FFFF]: |
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* Memory with Normal type, not shareable, non-cacheable |
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*/ |
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MPU_REGION_ENTRY("ITCM", REGION_ITCM_BASE_ADDRESS, |
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{ ARM_MPU_RASR(0, ARM_MPU_AP_FULL, |
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1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_128KB) }), |
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/* |
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* Region 2 QSPI[0x0800_0000 - 0x0FFF_FFFF]: |
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* Memory with Normal type, not shareable, cacheable |
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*/ |
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MPU_REGION_ENTRY("QSPI", REGION_QSPI_BASE_ADDRESS, |
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{ ARM_MPU_RASR(0, ARM_MPU_AP_FULL, |
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1, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128MB) }), |
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/* |
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* Region 3 DTCM[0x2000_0000 - 0x2002_0000]: |
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* Memory with Normal type, not shareable, non-cacheable |
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*/ |
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MPU_REGION_ENTRY("DTCM", REGION_DTCM_BASE_ADDRESS, |
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{ ARM_MPU_RASR(0, ARM_MPU_AP_FULL, |
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1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_128KB) }), |
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/* |
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* Region 4 DDR[0x4000_0000 - 0x8000_0000]: |
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* Memory with Normal type, not shareable, non-cacheable |
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*/ |
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MPU_REGION_ENTRY("DDR", REGION_DDR_BASE_ADDRESS, |
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{ ARM_MPU_RASR(0, ARM_MPU_AP_FULL, |
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1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB) }), |
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/* |
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* Non-cacheable area is provided in DDR memory, the DDR region [0x80000000 ~ 0x81000000] |
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* (please see the imx8mp-evk-rpmsg.dts) totally 16MB is reserved for CM7 core. You can put |
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* global or static uninitialized variables in NonCacheable section(initialized variables in |
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* NonCacheable.init section) to make them uncacheable. Since the base address of MPU region |
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* should be multiples of region size, to make it simple, the MPU region 5 set the address |
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* space 0x80000000 ~ 0xBFFFFFFF to be non-cacheable. Then MPU region 6 set the text and |
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* data section to be cacheable if the program running on DDR. The cacheable area base |
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* address should be multiples of its size in linker file, they can be modified per your |
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* needs. |
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* |
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* Region 5 DDR[0x8000_0000 - 0xBFFFFFFF]: |
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* Memory with Normal type, not shareable, non-cacheable |
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*/ |
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MPU_REGION_ENTRY("DDR2", REGION_DDR2_BASE_ADDRESS, |
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{ ARM_MPU_RASR(0, ARM_MPU_AP_FULL, |
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1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB) }), |
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#if defined(CONFIG_CODE_DDR) |
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/* If run on DDR, configure text and data section to be cacheable */ |
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MPU_REGION_ENTRY("DDR_NONCACHE", REGION_DDR_NONCACHE_BASE_ADDRESS, |
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{ ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, |
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0, 1, 1, 0, REGION_DDR_NONCACHE_SIZE) }), |
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#endif |
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}; |
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const struct arm_mpu_config mpu_config = { |
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.num_regions = ARRAY_SIZE(mpu_regions), |
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.mpu_regions = mpu_regions, |
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};
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