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42 lines
706 B
42 lines
706 B
/* |
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* Copyright 2023 NXP |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/ { |
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aliases { |
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sram-ext = &is66wvq8m4; |
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}; |
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}; |
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&is66wvq8m4 { |
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status = "okay"; |
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}; |
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&pinctrl { |
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pinmux_flexspi_safe: pinmux-flexspi-safe { |
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group0 { |
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pinmux = <IO_MUX_QUAD_SPI_PSRAM_IO35 |
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IO_MUX_QUAD_SPI_PSRAM_IO36 |
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IO_MUX_QUAD_SPI_PSRAM_IO38 |
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IO_MUX_QUAD_SPI_PSRAM_IO39 |
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IO_MUX_QUAD_SPI_PSRAM_IO40 |
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IO_MUX_QUAD_SPI_PSRAM_IO41>; |
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slew-rate = "normal"; |
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}; |
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group1 { |
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pinmux = <IO_MUX_QUAD_SPI_PSRAM_IO37>; |
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slew-rate = "normal"; |
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bias-pull-down; |
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}; |
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}; |
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}; |
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/* Override pin control state to use one that only changes the PSRAM pin |
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* configuration |
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*/ |
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&flexspi { |
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pinctrl-0 = <&pinmux_flexspi_safe>; |
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};
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