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49 lines
1.5 KiB
49 lines
1.5 KiB
# Copyright (c) 2022 Meta |
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# SPDX-License-Identifier: Apache-2.0 |
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description: Lattice iCE40 FPGA base |
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compatible: "lattice,ice40-fpga-base" |
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include: spi-device.yaml |
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properties: |
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cdone-gpios: |
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type: phandle-array |
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required: true |
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description: | |
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Configuration Done output from iCE40. |
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Example usage: |
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cdone-gpios = <&gpio0 0 0>; |
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creset-gpios: |
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type: phandle-array |
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required: true |
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description: | |
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Configuration Reset input on iCE40. |
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Example usage: |
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creset-gpios = <&gpio0 1 GPIO_PUSH_PULL); |
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creset-delay-us: |
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type: int |
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default: 1 |
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description: | |
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Delay (in microseconds) between asserting CRESET_B and releasing CRESET_B. |
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The datasheet specifies a minimum of 200ns, therefore the default is set |
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to 1us. |
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config-delay-us: |
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type: int |
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default: 1200 |
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description: | |
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Delay (in microseconds) after releasing CRESET_B to clear internal configuration memory. |
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The datasheet specifies a minimum of 1200us, which is the default. |
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leading-clocks: |
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type: int |
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default: 8 |
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description: | |
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Prior to sending the bitstream, issue this number of leading clocks with SPI_CS pulled high. |
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The datasheet specifies 8 dummy cycles, which is the default. |
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trailing-clocks: |
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type: int |
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default: 49 |
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description: | |
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After sending the bitstream, issue this number of trailing clocks with SPI_CS pulled high. |
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The datasheet specifies 49 dummy cycles, which is the default.
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