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67 lines
1.7 KiB
67 lines
1.7 KiB
/* |
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* Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk> |
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* Copyright (c) 2022 NXP |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT openisa_rv32m1_pinmux |
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#include <zephyr/drivers/pinctrl.h> |
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#include <fsl_clock.h> |
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#include <soc.h> |
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/* Port register addresses. */ |
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static PORT_Type *ports[] = { |
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(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porta)), |
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(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portb)), |
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(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portc)), |
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(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portd)), |
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(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porte)), |
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}; |
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#define PIN(mux) (((mux) & 0xFC00000) >> 22) |
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#define PORT(mux) (((mux) & 0xF0000000) >> 28) |
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#define PINCFG(mux) ((mux) & Z_PINCTRL_RV32M1_PCR_MASK) |
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struct pinctrl_rv32m1_config { |
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clock_ip_name_t clock_ip_name; |
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}; |
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, |
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uintptr_t reg) |
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{ |
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for (uint8_t i = 0; i < pin_cnt; i++) { |
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PORT_Type *base = ports[PORT(pins[i])]; |
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uint8_t pin = PIN(pins[i]); |
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uint16_t mux = PINCFG(pins[i]); |
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base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_RV32M1_PCR_MASK)) | mux; |
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} |
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return 0; |
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} |
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static int pinctrl_rv32m1_init(const struct device *dev) |
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{ |
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const struct pinctrl_rv32m1_config *config = dev->config; |
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CLOCK_EnableClock(config->clock_ip_name); |
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return 0; |
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} |
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#define PINCTRL_RV32M1_INIT(n) \ |
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static const struct pinctrl_rv32m1_config pinctrl_rv32m1_##n##_config = {\ |
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.clock_ip_name = INST_DT_CLOCK_IP_NAME(n), \ |
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}; \ |
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\ |
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DEVICE_DT_INST_DEFINE(n, \ |
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&pinctrl_rv32m1_init, \ |
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NULL, \ |
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NULL, &pinctrl_rv32m1_##n##_config, \ |
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PRE_KERNEL_1, \ |
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CONFIG_PINCTRL_RV32M1_INIT_PRIORITY, \ |
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NULL); |
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DT_INST_FOREACH_STATUS_OKAY(PINCTRL_RV32M1_INIT)
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