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102 lines
3.2 KiB
102 lines
3.2 KiB
/* |
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* Copyright 2022, 2024-2025 NXP |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <zephyr/arch/cpu.h> |
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#include <zephyr/init.h> |
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#include <zephyr/drivers/pinctrl.h> |
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, |
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uintptr_t reg) |
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{ |
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/* configure all pins */ |
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for (uint8_t i = 0U; i < pin_cnt; i++) { |
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uint32_t mux_register = pins[i].pinmux.mux_register; |
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uint32_t mux_mode = pins[i].pinmux.mux_mode; |
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uint32_t input_register = pins[i].pinmux.input_register; |
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uint32_t input_daisy = pins[i].pinmux.input_daisy; |
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uint32_t config_register = pins[i].pinmux.config_register; |
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uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags; |
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#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX) |
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volatile uint32_t *gpr_register = |
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(volatile uint32_t *)((uintptr_t)pins[i].pinmux.gpr_register); |
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if (gpr_register) { |
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/* Set or clear specified GPR bit for this mux */ |
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if (pins[i].pinmux.gpr_val) { |
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*gpr_register |= |
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(pins[i].pinmux.gpr_val << pins[i].pinmux.gpr_shift); |
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} else { |
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*gpr_register &= ~(0x1 << pins[i].pinmux.gpr_shift); |
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} |
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} |
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#endif |
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#if defined(CONFIG_SOC_MIMX9352) || defined(CONFIG_SOC_MIMX9131) |
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sys_write32(IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) | |
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IOMUXC1_SW_MUX_CTL_PAD_SION(MCUX_IMX_INPUT_ENABLE(pin_ctrl_flags)), |
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(mem_addr_t)mux_register); |
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if (input_register) { |
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sys_write32(IOMUXC1_SELECT_INPUT_DAISY(input_daisy), |
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(mem_addr_t)input_register); |
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} |
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if (config_register) { |
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sys_write32(pin_ctrl_flags & (~(0x1 << MCUX_IMX_INPUT_ENABLE_SHIFT)), |
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(mem_addr_t)config_register); |
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} |
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#elif defined(CONFIG_SOC_MIMX8UD7) |
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if (mux_register == config_register) { |
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sys_write32(IOMUXC_PCR_MUX_MODE(mux_mode) | |
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pin_ctrl_flags, (mem_addr_t)mux_register); |
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} else { |
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sys_write32(IOMUXC_PCR_MUX_MODE(mux_mode), |
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(mem_addr_t)mux_register); |
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if (config_register) { |
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sys_write32(pin_ctrl_flags, (mem_addr_t)config_register); |
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} |
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} |
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if (input_register) { |
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sys_write32(IOMUXC_PSMI_SSS(input_daisy), (mem_addr_t)input_register); |
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} |
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#else |
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sys_write32( |
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IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) | |
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IOMUXC_SW_MUX_CTL_PAD_SION(MCUX_IMX_INPUT_ENABLE(pin_ctrl_flags)), |
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(mem_addr_t)mux_register); |
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if (input_register) { |
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sys_write32(IOMUXC_SELECT_INPUT_DAISY(input_daisy), |
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(mem_addr_t)input_register); |
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} |
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if (config_register) { |
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sys_write32(pin_ctrl_flags & (~(0x1 << MCUX_IMX_INPUT_ENABLE_SHIFT)), |
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config_register); |
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} |
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#endif |
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} |
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return 0; |
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} |
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static int imx_pinctrl_init(void) |
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{ |
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#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX) |
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CLOCK_EnableClock(kCLOCK_Iomuxc); |
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#ifdef CONFIG_SOC_SERIES_IMXRT10XX |
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CLOCK_EnableClock(kCLOCK_IomuxcSnvs); |
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CLOCK_EnableClock(kCLOCK_IomuxcGpr); |
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#elif defined(CONFIG_SOC_SERIES_IMXRT11XX) |
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CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr); |
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#endif /* CONFIG_SOC_SERIES_IMXRT10XX */ |
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#elif defined(CONFIG_SOC_MIMX8MQ6) |
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CLOCK_EnableClock(kCLOCK_Iomux); |
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#endif /* CONFIG_SOC_SERIES_IMXRT10XX || CONFIG_SOC_SERIES_IMXRT11XX */ |
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#if defined(CONFIG_SOC_SERIES_IMXRT118X) |
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CLOCK_EnableClock(kCLOCK_Iomuxc1); |
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CLOCK_EnableClock(kCLOCK_Iomuxc2); |
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#endif /* CONFIG_SOC_SERIES_IMXRT118X */ |
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return 0; |
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} |
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SYS_INIT(imx_pinctrl_init, PRE_KERNEL_1, 0);
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