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312 lines
7.2 KiB
312 lines
7.2 KiB
/* |
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* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/* Include esp-idf headers first to avoid redefining BIT() macro */ |
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#include <hal/gpio_ll.h> |
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#include <hal/rtc_io_hal.h> |
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#include <soc.h> |
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#include <zephyr/drivers/pinctrl.h> |
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#include <zephyr/drivers/pinctrl/pinctrl_esp32_common.h> |
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#ifdef CONFIG_SOC_SERIES_ESP32C2 |
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#define out out.val |
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#define in in.val |
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#define out_w1ts out_w1ts.val |
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#define out_w1tc out_w1tc.val |
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#elif CONFIG_SOC_SERIES_ESP32C3 |
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/* gpio structs in esp32c3 series are different from xtensa ones */ |
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#define out out.data |
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#define in in.data |
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#define out_w1ts out_w1ts.val |
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#define out_w1tc out_w1tc.val |
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#elif CONFIG_SOC_SERIES_ESP32C6 |
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/* gpio structs in esp32c6 are also different */ |
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#define out out.out_data_orig |
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#define in in.in_data_next |
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#define out_w1ts out_w1ts.val |
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#define out_w1tc out_w1tc.val |
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#endif |
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#ifndef SOC_GPIO_SUPPORT_RTC_INDEPENDENT |
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#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT 0 |
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#endif |
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#define ESP32_INVALID_PORT_ADDR 0UL |
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#define ESP32_GPIO_PORT_ADDR(nodelabel) \ |
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COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \ |
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(DT_REG_ADDR(DT_NODELABEL(nodelabel)),), \ |
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(ESP32_INVALID_PORT_ADDR)) |
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/** |
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* @brief Array containing each GPIO port address. |
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* |
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* Entries will be an invalid address if the port is not enabled. |
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*/ |
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static const uint32_t esp32_gpio_ports_addrs[] = { |
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ESP32_GPIO_PORT_ADDR(gpio0) |
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ESP32_GPIO_PORT_ADDR(gpio1) |
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}; |
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/** Number of GPIO ports. */ |
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static const size_t esp32_gpio_ports_cnt = ARRAY_SIZE(esp32_gpio_ports_addrs); |
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static inline bool rtc_gpio_is_valid_gpio(uint32_t gpio_num) |
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{ |
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#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED |
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return (gpio_num < SOC_GPIO_PIN_COUNT && rtc_io_num_map[gpio_num] >= 0); |
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#else |
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return false; |
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#endif |
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} |
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static inline bool esp32_pin_is_valid(uint32_t pin) |
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{ |
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return ((BIT(pin) & SOC_GPIO_VALID_GPIO_MASK) != 0); |
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} |
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static inline bool esp32_pin_is_output_capable(uint32_t pin) |
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{ |
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return ((BIT(pin) & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) != 0); |
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} |
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static int esp32_pin_apply_config(uint32_t pin, uint32_t flags) |
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{ |
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gpio_dev_t *const gpio_base = (gpio_dev_t *)DT_REG_ADDR(DT_NODELABEL(gpio0)); |
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uint32_t io_pin = (uint32_t) pin + ((ESP32_PORT_IDX(pin) == 1 && pin < 32) ? 32 : 0); |
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int ret = 0; |
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if (!esp32_pin_is_valid(io_pin)) { |
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return -EINVAL; |
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} |
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#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED |
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if (rtc_gpio_is_valid_gpio(io_pin)) { |
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rtcio_hal_function_select(rtc_io_num_map[io_pin], RTCIO_FUNC_DIGITAL); |
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} |
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#endif |
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if (io_pin >= GPIO_NUM_MAX) { |
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ret = -EINVAL; |
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goto end; |
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} |
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/* Set pin function as GPIO */ |
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gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[io_pin], PIN_FUNC_GPIO); |
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if (flags & ESP32_PULL_UP_FLAG) { |
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if (!rtc_gpio_is_valid_gpio(io_pin) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) { |
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gpio_ll_pulldown_dis(&GPIO, io_pin); |
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gpio_ll_pullup_en(&GPIO, io_pin); |
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} else { |
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#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED |
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int rtcio_num = rtc_io_num_map[io_pin]; |
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rtcio_hal_pulldown_disable(rtc_io_num_map[io_pin]); |
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if (rtc_io_desc[rtcio_num].pullup) { |
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rtcio_hal_pullup_enable(rtc_io_num_map[io_pin]); |
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} else { |
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ret = -ENOTSUP; |
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goto end; |
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} |
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#endif |
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} |
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} else if (flags & ESP32_PULL_DOWN_FLAG) { |
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if (!rtc_gpio_is_valid_gpio(io_pin) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) { |
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gpio_ll_pullup_dis(&GPIO, io_pin); |
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gpio_ll_pulldown_en(&GPIO, io_pin); |
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} else { |
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#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED |
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int rtcio_num = rtc_io_num_map[io_pin]; |
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rtcio_hal_pulldown_enable(rtc_io_num_map[io_pin]); |
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if (rtc_io_desc[rtcio_num].pullup) { |
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rtcio_hal_pullup_disable(rtc_io_num_map[io_pin]); |
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} else { |
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ret = -ENOTSUP; |
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goto end; |
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} |
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#endif |
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} |
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} |
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if (flags & ESP32_DIR_OUT_FLAG) { |
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if (!esp32_pin_is_output_capable(pin)) { |
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ret = -EINVAL; |
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goto end; |
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} |
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if (flags & ESP32_OPEN_DRAIN_FLAG) { |
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gpio_ll_od_enable(gpio_base, io_pin); |
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} else { |
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gpio_ll_od_disable(gpio_base, io_pin); |
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} |
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/* Set output pin initial value */ |
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if (flags & ESP32_PIN_OUT_HIGH_FLAG) { |
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gpio_ll_set_level(gpio_base, io_pin, 1); |
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} else if (flags & ESP32_PIN_OUT_LOW_FLAG) { |
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gpio_ll_set_level(gpio_base, io_pin, 0); |
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} |
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gpio_ll_output_enable(&GPIO, io_pin); |
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esp_rom_gpio_matrix_out(io_pin, SIG_GPIO_OUT_IDX, false, false); |
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} else { |
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if (!(flags & ESP32_PIN_OUT_EN_FLAG)) { |
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gpio_ll_output_disable(&GPIO, io_pin); |
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} |
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} |
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if (flags & ESP32_DIR_INP_FLAG) { |
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gpio_ll_input_enable(&GPIO, io_pin); |
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} else { |
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if (!(flags & ESP32_PIN_IN_EN_FLAG)) { |
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gpio_ll_input_disable(&GPIO, io_pin); |
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} |
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} |
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end: |
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return ret; |
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} |
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static int esp32_pin_configure(const uint32_t pin_mux, const uint32_t pin_cfg) |
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{ |
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uint32_t port_addr; |
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uint32_t pin_num = ESP32_PIN_NUM(pin_mux); |
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uint32_t sig_in = ESP32_PIN_SIGI(pin_mux); |
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uint32_t sig_out = ESP32_PIN_SIGO(pin_mux); |
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uint32_t flags = 0; |
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if (ESP32_PORT_IDX(pin_num) >= esp32_gpio_ports_cnt) { |
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return -EINVAL; |
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} |
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port_addr = esp32_gpio_ports_addrs[ESP32_PORT_IDX(pin_num)]; |
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if (port_addr == ESP32_INVALID_PORT_ADDR) { |
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return -EINVAL; |
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} |
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switch (ESP32_PIN_BIAS(pin_cfg)) { |
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case ESP32_PULL_UP: |
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flags |= ESP32_PULL_UP_FLAG; |
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break; |
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case ESP32_PULL_DOWN: |
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flags |= ESP32_PULL_DOWN_FLAG; |
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break; |
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default: |
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break; |
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} |
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switch (ESP32_PIN_DRV(pin_cfg)) { |
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case ESP32_PUSH_PULL: |
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flags |= ESP32_PUSH_PULL_FLAG; |
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break; |
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case ESP32_OPEN_DRAIN: |
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flags |= ESP32_OPEN_DRAIN_FLAG; |
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break; |
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default: |
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break; |
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} |
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if (sig_in == ESP_SIG_INVAL && sig_out == ESP_SIG_INVAL) { |
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return -ENOTSUP; |
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} |
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if (sig_in != ESP_SIG_INVAL) { |
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flags |= ESP32_DIR_INP_FLAG; |
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} |
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if (sig_out != ESP_SIG_INVAL) { |
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flags |= ESP32_DIR_OUT_FLAG; |
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} |
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switch (ESP32_PIN_MODE_OUT(pin_cfg)) { |
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case ESP32_PIN_OUT_HIGH: |
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flags |= ESP32_PIN_OUT_HIGH_FLAG; |
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break; |
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case ESP32_PIN_OUT_LOW: |
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flags |= ESP32_PIN_OUT_LOW_FLAG; |
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break; |
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default: |
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break; |
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} |
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switch (ESP32_PIN_EN_DIR(pin_cfg)) { |
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case ESP32_PIN_OUT_EN: |
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flags |= ESP32_PIN_OUT_EN_FLAG; |
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break; |
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case ESP32_PIN_IN_EN: |
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flags |= ESP32_PIN_IN_EN_FLAG; |
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break; |
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default: |
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break; |
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} |
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if (flags & ESP32_PIN_OUT_HIGH_FLAG) { |
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if (ESP32_PORT_IDX(pin_num) == 0) { |
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gpio_dev_t *const gpio_dev = |
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(gpio_dev_t *)DT_REG_ADDR(DT_NODELABEL(gpio0)); |
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gpio_dev->out_w1ts = BIT(pin_num); |
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1)) |
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} else { |
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gpio_dev_t *const gpio_dev = |
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(gpio_dev_t *)DT_REG_ADDR(DT_NODELABEL(gpio1)); |
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gpio_dev->out1_w1ts.data = BIT(pin_num - 32); |
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#endif |
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} |
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} |
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if (flags & ESP32_PIN_OUT_LOW_FLAG) { |
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if (ESP32_PORT_IDX(pin_num) == 0) { |
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gpio_dev_t *const gpio_dev = |
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(gpio_dev_t *)DT_REG_ADDR(DT_NODELABEL(gpio0)); |
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gpio_dev->out_w1tc = BIT(pin_num); |
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1)) |
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} else { |
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gpio_dev_t *const gpio_dev = |
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(gpio_dev_t *)DT_REG_ADDR(DT_NODELABEL(gpio1)); |
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gpio_dev->out1_w1tc.data = BIT(pin_num - 32); |
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#endif |
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} |
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} |
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esp32_pin_apply_config(pin_num, flags); |
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if (flags & ESP32_DIR_OUT_FLAG) { |
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esp_rom_gpio_matrix_out(pin_num, sig_out, 0, 0); |
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} |
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if (flags & ESP32_DIR_INP_FLAG) { |
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esp_rom_gpio_matrix_in(pin_num, sig_in, 0); |
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} |
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return 0; |
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} |
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, |
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uintptr_t reg) |
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{ |
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uint32_t pin_mux, pin_cfg; |
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int ret = 0; |
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ARG_UNUSED(reg); |
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for (uint8_t i = 0U; i < pin_cnt; i++) { |
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pin_mux = pins[i].pinmux; |
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pin_cfg = pins[i].pincfg; |
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ret = esp32_pin_configure(pin_mux, pin_cfg); |
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if (ret < 0) { |
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return ret; |
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} |
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} |
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return 0; |
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}
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