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125 lines
3.3 KiB
125 lines
3.3 KiB
/* ieee802154_mcxw.h - NXP MCXW 802.15.4 driver */ |
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/* |
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* Copyright 2025 NXP |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCXW_H_ |
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#define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCXW_H_ |
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#include <zephyr/net/ieee802154_radio.h> |
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#include "PhyInterface.h" |
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#define TX_ENCRYPT_DELAY_SYM 200 |
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#define DEFAULT_CHANNEL (11) |
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#define DEFAULT_CCA_MODE (gPhyCCAMode1_c) |
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#define IEEE802154_ACK_REQUEST (1 << 5) |
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#define IEEE802154_MIN_LENGTH (5) |
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#define IEEE802154_FRM_CTL_LO_OFFSET (0) |
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#define IEEE802154_DSN_OFFSET (2) |
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#define IEEE802154_FRM_TYPE_MASK (0x7) |
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#define IEEE802154_FRM_TYPE_ACK (0x2) |
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#define IEEE802154_SYMBOL_TIME_US (16) |
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#define IEEE802154_TURNAROUND_LEN_SYM (12) |
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#define IEEE802154_CCA_LEN_SYM (8) |
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#define IEEE802154_PHY_SHR_LEN_SYM (10) |
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#define IEEE802154_IMM_ACK_WAIT_SYM (54) |
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#define IEEE802154_ENH_ACK_WAIT_SYM (90) |
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#define NMAX_RXRING_BUFFERS (8) |
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#define RX_ON_IDLE_START (1) |
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#define RX_ON_IDLE_STOP (0) |
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#define PHY_TMR_MAX_VALUE (0x00FFFFFF) |
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/* The Uncertainty of the scheduling CSL of transmission by the parent, in ±10 us units. */ |
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#define CSL_UNCERT 32 |
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#define RADIO_SYMBOLS_PER_OCTET (2) |
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typedef enum mcxw_radio_state { |
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RADIO_STATE_DISABLED = 0, |
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RADIO_STATE_SLEEP = 1, |
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RADIO_STATE_RECEIVE = 2, |
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RADIO_STATE_TRANSMIT = 3, |
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RADIO_STATE_INVALID = 255, |
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} mcxw_radio_state; |
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typedef struct mcxw_rx_frame { |
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uint8_t *psdu; |
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uint8_t length; |
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int8_t rssi; |
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uint8_t lqi; |
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uint32_t timestamp; |
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bool ack_fpb; |
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bool ack_seb; |
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uint64_t time; |
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void *phy_buffer; |
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uint8_t channel; |
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} mcxw_rx_frame; |
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typedef struct mcxw_tx_frame { |
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uint8_t *psdu; |
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uint8_t length; |
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uint32_t tx_delay; |
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uint32_t tx_delay_base; |
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bool sec_processed; |
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bool hdr_updated; |
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} mcxw_tx_frame; |
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struct mcxw_context { |
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/* Pointer to the network interface. */ |
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struct net_if *iface; |
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/* Pointer to the LPTMR counter device structure*/ |
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const struct device *counter; |
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/* 802.15.4 HW address. */ |
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uint8_t mac[8]; |
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/* RX thread stack. */ |
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K_KERNEL_STACK_MEMBER(rx_stack, CONFIG_IEEE802154_MCXW_RX_STACK_SIZE); |
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/* RX thread control block. */ |
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struct k_thread rx_thread; |
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/* RX message queue */ |
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struct k_msgq rx_msgq; |
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/* RX message queue buffer */ |
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char rx_msgq_buffer[NMAX_RXRING_BUFFERS * sizeof(mcxw_rx_frame)]; |
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/* TX synchronization semaphore */ |
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struct k_sem tx_wait; |
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/* TX synchronization semaphore */ |
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struct k_sem cca_wait; |
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/* Radio state */ |
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mcxw_radio_state state; |
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/* Pan ID */ |
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uint16_t pan_id; |
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/* Channel */ |
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uint8_t channel; |
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/* Maximum energy detected during ED scan */ |
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int8_t max_ed; |
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/* TX power level */ |
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int8_t tx_pwr_lvl; |
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/* Enery detect */ |
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energy_scan_done_cb_t energy_scan_done; |
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/* TX Status */ |
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int tx_status; |
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/* TX frame */ |
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mcxw_tx_frame tx_frame; |
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/* TX data */ |
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uint8_t tx_data[sizeof(macToPdDataMessage_t) + IEEE802154_MAX_PHY_PACKET_SIZE]; |
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/* RX mode */ |
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uint32_t rx_mode; |
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/* RX ACK buffers */ |
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mcxw_rx_frame rx_ack_frame; |
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/* RX ACK data */ |
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uint8_t rx_ack_data[IEEE802154_MAX_PHY_PACKET_SIZE]; |
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/* CSL period */ |
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uint32_t csl_period; |
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/* CSL sample time in microseconds */ |
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uint32_t csl_sample_time; |
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/* PHY context */ |
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uint8_t ot_phy_ctx; |
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}; |
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#endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCXW_H_ */
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