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374 lines
8.8 KiB
374 lines
8.8 KiB
/* |
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* Copyright (c) 2017 Intel Corporation |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT espressif_esp32_gpio |
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/* Include esp-idf headers first to avoid redefining BIT() macro */ |
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#include <soc/dport_reg.h> |
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#include <soc/gpio_reg.h> |
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#include <soc/io_mux_reg.h> |
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#include <soc/soc.h> |
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#include <soc.h> |
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#include <errno.h> |
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#include <device.h> |
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#include <drivers/gpio.h> |
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#include <kernel.h> |
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#include <sys/util.h> |
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#include <drivers/pinmux.h> |
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#include "gpio_utils.h" |
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#define GET_GPIO_PIN_REG(pin) ((uint32_t *)GPIO_REG(pin)) |
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/* ESP3 TRM v4.0 and gpio_reg.h header both incorrectly identify bit3 |
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* as being the bit selecting PRO CPU interrupt enable. It's actually |
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* bit2. bit4 and bit5 are also shifted. |
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*/ |
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#define GPIO_CPU0_INT_ENABLE (BIT(2) << GPIO_PIN_INT_ENA_S) |
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/* ESP3 TRM table 8: CPU Interrupts |
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* |
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* Edge-triggered are: 10, 22, 28, 30 |
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* Level-triggered are: 0-5, 8, 9, 12, 13, 17-21, 23-27, 31 |
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*/ |
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#define ESP32_IRQ_EDGE_TRIG 0x50400400 |
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#define ESP32_IRQ_LEVEL_TRIG 0x8fbe333f |
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struct gpio_esp32_data { |
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/* gpio_driver_data needs to be first */ |
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struct gpio_driver_data common; |
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const struct device *pinmux; |
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struct { |
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volatile uint32_t *set_reg; |
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volatile uint32_t *clear_reg; |
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volatile uint32_t *input_reg; |
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volatile uint32_t *output_reg; |
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volatile uint32_t *irq_status_reg; |
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volatile uint32_t *irq_ack_reg; |
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int pin_offset; |
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} port; |
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sys_slist_t cb; |
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}; |
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static int gpio_esp32_config(const struct device *dev, |
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gpio_pin_t pin, |
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gpio_flags_t flags) |
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{ |
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struct gpio_esp32_data *data = dev->data; |
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uint32_t io_pin = pin + data->port.pin_offset; /* Range from 0 - 39 */ |
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uint32_t *reg = GET_GPIO_PIN_REG(io_pin); |
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uint32_t func; |
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int r; |
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/* Query pinmux to validate pin number. */ |
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r = pinmux_pin_get(data->pinmux, io_pin, &func); |
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if (r < 0) { |
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return r; |
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} |
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/* Set pin function as GPIO */ |
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pinmux_pin_set(data->pinmux, io_pin, PIN_FUNC_GPIO); |
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if (flags & GPIO_PULL_UP) { |
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pinmux_pin_pullup(data->pinmux, io_pin, PINMUX_PULLUP_ENABLE); |
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} else if (flags & GPIO_PULL_DOWN) { |
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pinmux_pin_pullup(data->pinmux, io_pin, PINMUX_PULLUP_DISABLE); |
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} |
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if (flags & GPIO_OUTPUT) { |
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if (flags & GPIO_SINGLE_ENDED) { |
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if (flags & GPIO_LINE_OPEN_DRAIN) { |
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*reg |= GPIO_PIN_PAD_DRIVER; |
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} else { |
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r = -ENOTSUP; |
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} |
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} else { |
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*reg &= ~GPIO_PIN_PAD_DRIVER; |
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} |
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/* Set output pin initial value */ |
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if (flags & GPIO_OUTPUT_INIT_HIGH) { |
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*data->port.set_reg = BIT(pin); |
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} else if (flags & GPIO_OUTPUT_INIT_LOW) { |
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*data->port.clear_reg = BIT(pin); |
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} |
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r = pinmux_pin_input_enable(data->pinmux, io_pin, |
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PINMUX_OUTPUT_ENABLED); |
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if (r < 0) { |
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return r; |
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} |
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} else { /* Input */ |
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pinmux_pin_input_enable(data->pinmux, io_pin, |
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PINMUX_INPUT_ENABLED); |
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} |
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return 0; |
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} |
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static int gpio_esp32_port_get_raw(const struct device *port, uint32_t *value) |
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{ |
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struct gpio_esp32_data *data = port->data; |
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*value = *data->port.input_reg; |
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return 0; |
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} |
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static int gpio_esp32_port_set_masked_raw(const struct device *port, |
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uint32_t mask, uint32_t value) |
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{ |
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struct gpio_esp32_data *data = port->data; |
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uint32_t key; |
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key = irq_lock(); |
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*data->port.output_reg = (*data->port.output_reg & ~mask) |
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| (mask & value); |
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irq_unlock(key); |
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return 0; |
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} |
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static int gpio_esp32_port_set_bits_raw(const struct device *port, |
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uint32_t pins) |
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{ |
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struct gpio_esp32_data *data = port->data; |
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*data->port.set_reg = pins; |
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return 0; |
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} |
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static int gpio_esp32_port_clear_bits_raw(const struct device *port, |
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uint32_t pins) |
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{ |
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struct gpio_esp32_data *data = port->data; |
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*data->port.clear_reg = pins; |
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return 0; |
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} |
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static int gpio_esp32_port_toggle_bits(const struct device *port, |
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uint32_t pins) |
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{ |
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struct gpio_esp32_data *data = port->data; |
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uint32_t key; |
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key = irq_lock(); |
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*data->port.output_reg = (*data->port.output_reg ^ pins); |
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irq_unlock(key); |
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return 0; |
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} |
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static int convert_int_type(enum gpio_int_mode mode, |
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enum gpio_int_trig trig) |
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{ |
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/* Reference: "ESP32 Technical Reference Manual" > "IO_MUX and |
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* GPIO matrix" > "GPIO_PINn_INT_TYPE". |
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*/ |
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if (mode == GPIO_INT_MODE_DISABLED) { |
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return 0; /* Disables interrupt for a pin. */ |
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} |
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if (mode == GPIO_INT_MODE_LEVEL) { |
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if ((ESP32_IRQ_LEVEL_TRIG & BIT(CONFIG_GPIO_ESP32_IRQ)) == 0) { |
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return -ENOTSUP; |
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} |
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switch (trig) { |
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case GPIO_INT_TRIG_LOW: |
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return 4; |
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case GPIO_INT_TRIG_HIGH: |
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return 5; |
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default: |
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return -EINVAL; |
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} |
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} else { /* edge interrupts */ |
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if ((ESP32_IRQ_EDGE_TRIG & BIT(CONFIG_GPIO_ESP32_IRQ)) == 0) { |
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return -ENOTSUP; |
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} |
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switch (trig) { |
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case GPIO_INT_TRIG_HIGH: |
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return 1; |
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case GPIO_INT_TRIG_LOW: |
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return 2; |
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case GPIO_INT_TRIG_BOTH: |
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/* This is supposed to work but doesn't */ |
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return -ENOTSUP; /* 3 == any edge */ |
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default: |
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return -EINVAL; |
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} |
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} |
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/* Any other type of interrupt triggering is invalid. */ |
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return -EINVAL; |
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} |
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static int gpio_esp32_pin_interrupt_configure(const struct device *port, |
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gpio_pin_t pin, |
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enum gpio_int_mode mode, |
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enum gpio_int_trig trig) |
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{ |
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struct gpio_esp32_data *data = port->data; |
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uint32_t io_pin = pin + data->port.pin_offset; /* Range from 0 - 39 */ |
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uint32_t *reg = GET_GPIO_PIN_REG(io_pin); |
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int intr_trig_mode = convert_int_type(mode, trig); |
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uint32_t reg_val; |
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uint32_t key; |
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if (intr_trig_mode < 0) { |
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return intr_trig_mode; |
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} |
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key = irq_lock(); |
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reg_val = *reg; |
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reg_val &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M); |
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/* Enable Interrupt on CPU0 (PRO_CPU) */ |
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reg_val |= GPIO_CPU0_INT_ENABLE; |
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/* Interrupt triggering mode */ |
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reg_val |= intr_trig_mode << GPIO_PIN_INT_TYPE_S; |
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*reg = reg_val; |
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irq_unlock(key); |
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return 0; |
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} |
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static int gpio_esp32_manage_callback(const struct device *dev, |
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struct gpio_callback *callback, |
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bool set) |
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{ |
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struct gpio_esp32_data *data = dev->data; |
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return gpio_manage_callback(&data->cb, callback, set); |
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} |
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static void gpio_esp32_fire_callbacks(const struct device *device) |
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{ |
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struct gpio_esp32_data *data = device->data; |
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uint32_t irq_status = *data->port.irq_status_reg; |
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*data->port.irq_ack_reg = irq_status; |
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gpio_fire_callbacks(&data->cb, device, irq_status); |
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} |
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static void gpio_esp32_isr(const void *param); |
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static int gpio_esp32_init(const struct device *device) |
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{ |
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struct gpio_esp32_data *data = device->data; |
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static bool isr_connected; |
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data->pinmux = DEVICE_DT_GET(DT_NODELABEL(pinmux)); |
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if ((data->pinmux != NULL) |
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&& !device_is_ready(data->pinmux)) { |
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data->pinmux = NULL; |
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} |
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if (!data->pinmux) { |
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return -ENOTSUP; |
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} |
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if (!isr_connected) { |
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irq_disable(CONFIG_GPIO_ESP32_IRQ); |
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IRQ_CONNECT(CONFIG_GPIO_ESP32_IRQ, 1, gpio_esp32_isr, |
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NULL, 0); |
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esp32_rom_intr_matrix_set(0, ETS_GPIO_INTR_SOURCE, |
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CONFIG_GPIO_ESP32_IRQ); |
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irq_enable(CONFIG_GPIO_ESP32_IRQ); |
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isr_connected = true; |
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} |
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return 0; |
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} |
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static const struct gpio_driver_api gpio_esp32_driver = { |
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.pin_configure = gpio_esp32_config, |
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.port_get_raw = gpio_esp32_port_get_raw, |
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.port_set_masked_raw = gpio_esp32_port_set_masked_raw, |
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.port_set_bits_raw = gpio_esp32_port_set_bits_raw, |
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.port_clear_bits_raw = gpio_esp32_port_clear_bits_raw, |
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.port_toggle_bits = gpio_esp32_port_toggle_bits, |
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.pin_interrupt_configure = gpio_esp32_pin_interrupt_configure, |
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.manage_callback = gpio_esp32_manage_callback, |
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}; |
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#if defined(CONFIG_GPIO_ESP32_0) |
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static struct gpio_esp32_data gpio_0_data = { /* 0..31 */ |
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.port = { |
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.set_reg = (uint32_t *)GPIO_OUT_W1TS_REG, |
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.clear_reg = (uint32_t *)GPIO_OUT_W1TC_REG, |
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.input_reg = (uint32_t *)GPIO_IN_REG, |
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.output_reg = (uint32_t *)GPIO_OUT_REG, |
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.irq_status_reg = (uint32_t *)GPIO_STATUS_REG, |
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.irq_ack_reg = (uint32_t *)GPIO_STATUS_W1TC_REG, |
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.pin_offset = 0, |
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} |
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}; |
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#endif |
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#if defined(CONFIG_GPIO_ESP32_1) |
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static struct gpio_esp32_data gpio_1_data = { /* 32..39 */ |
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.port = { |
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.set_reg = (uint32_t *)GPIO_OUT1_W1TS_REG, |
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.clear_reg = (uint32_t *)GPIO_OUT1_W1TC_REG, |
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.input_reg = (uint32_t *)GPIO_IN1_REG, |
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.output_reg = (uint32_t *)GPIO_OUT1_REG, |
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.irq_status_reg = (uint32_t *)GPIO_STATUS1_REG, |
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.irq_ack_reg = (uint32_t *)GPIO_STATUS1_W1TC_REG, |
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.pin_offset = 32, |
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} |
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}; |
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#endif |
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#define GPIO_DEVICE_INIT(_id) \ |
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static struct gpio_driver_config gpio_##_id##_cfg = { \ |
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(_id), \ |
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}; \ |
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DEVICE_DT_INST_DEFINE(_id, \ |
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gpio_esp32_init, \ |
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device_pm_control_nop, \ |
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&gpio_##_id##_data, &gpio_##_id##_cfg, \ |
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POST_KERNEL, \ |
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \ |
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&gpio_esp32_driver) |
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/* GPIOs are divided in two groups for ESP32 because the callback |
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* API works with 32-bit bitmasks to manage interrupt callbacks, |
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* and the device has 40 GPIO pins. |
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*/ |
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#if defined(CONFIG_GPIO_ESP32_0) |
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GPIO_DEVICE_INIT(0); |
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#endif |
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#if defined(CONFIG_GPIO_ESP32_1) |
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GPIO_DEVICE_INIT(1); |
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#endif |
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static void gpio_esp32_isr(const void *param) |
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{ |
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#if defined(CONFIG_GPIO_ESP32_0) |
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gpio_esp32_fire_callbacks(DEVICE_DT_INST_GET(0)); |
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#endif |
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#if defined(CONFIG_GPIO_ESP32_1) |
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gpio_esp32_fire_callbacks(DEVICE_DT_INST_GET(1)); |
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#endif |
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ARG_UNUSED(param); |
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}
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