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43 lines
1.5 KiB
43 lines
1.5 KiB
/* |
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* Copyright (c) 2023 Rivos Inc. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <zephyr/arch/cpu.h> |
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#include <zephyr/devicetree.h> |
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#include <zephyr/init.h> |
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/* OpenTitan power management regs. */ |
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#define PWRMGR_BASE (DT_REG_ADDR(DT_NODELABEL(pwrmgr))) |
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#define PWRMGR_CFG_CDC_SYNC_REG_OFFSET 0x018 |
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#define PWRMGR_RESET_EN_REG_OFFSET 0x02c |
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#define PWRMGR_RESET_EN_WDOG_SRC_MASK 0x002 |
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/* Ibex timer registers. */ |
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#define RV_TIMER_BASE (DT_REG_ADDR(DT_NODELABEL(mtimer))) |
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#define RV_TIMER_CTRL_REG_OFFSET 0x004 |
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#define RV_TIMER_INTR_ENABLE_REG_OFFSET 0x100 |
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#define RV_TIMER_CFG0_REG_OFFSET 0x10c |
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#define RV_TIMER_CFG0_PRESCALE_MASK 0xfff |
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#define RV_TIMER_CFG0_PRESCALE_OFFSET 0 |
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#define RV_TIMER_CFG0_STEP_MASK 0xff |
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#define RV_TIMER_CFG0_STEP_OFFSET 16 |
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#define RV_TIMER_LOWER0_OFFSET 0x110 |
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#define RV_TIMER_COMPARE_LOWER0_OFFSET 0x118 |
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void soc_early_init_hook(void) |
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{ |
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/* Enable the watchdog reset (bit 1). */ |
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sys_write32(2u, PWRMGR_BASE + PWRMGR_RESET_EN_REG_OFFSET); |
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/* Write CFG_CDC_SYNC to commit change. */ |
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sys_write32(1u, PWRMGR_BASE + PWRMGR_CFG_CDC_SYNC_REG_OFFSET); |
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/* Poll CFG_CDC_SYNC register until it reads 0. */ |
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while (sys_read32(PWRMGR_BASE + PWRMGR_CFG_CDC_SYNC_REG_OFFSET)) { |
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} |
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/* Initialize the Machine Timer, so it behaves as a regular one. */ |
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sys_write32(1u, RV_TIMER_BASE + RV_TIMER_CTRL_REG_OFFSET); |
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/* Enable timer interrupts. */ |
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sys_write32(1u, RV_TIMER_BASE + RV_TIMER_INTR_ENABLE_REG_OFFSET); |
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}
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