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414 lines
11 KiB
414 lines
11 KiB
/* |
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* Copyright 2022-2024 NXP |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT nxp_s32_swt |
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#include <zephyr/kernel.h> |
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#include <zephyr/drivers/watchdog.h> |
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#include <zephyr/drivers/clock_control.h> |
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#include <zephyr/irq.h> |
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#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL |
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#include <zephyr/logging/log.h> |
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LOG_MODULE_REGISTER(swt_nxp_s32); |
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/* Software Watchdog Timer (SWT) register definitions */ |
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/* Control */ |
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#define SWT_CR 0x0 |
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#define SWT_CR_WEN_MASK BIT(0) |
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#define SWT_CR_WEN(v) FIELD_PREP(SWT_CR_WEN_MASK, (v)) |
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#define SWT_CR_FRZ_MASK BIT(1) |
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#define SWT_CR_FRZ(v) FIELD_PREP(SWT_CR_FRZ_MASK, (v)) |
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#define SWT_CR_STP_MASK BIT(2) |
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#define SWT_CR_STP(v) FIELD_PREP(SWT_CR_STP_MASK, (v)) |
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#define SWT_CR_SLK_MASK BIT(4) |
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#define SWT_CR_SLK(v) FIELD_PREP(SWT_CR_SLK_MASK, (v)) |
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#define SWT_CR_HLK_MASK BIT(5) |
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#define SWT_CR_HLK(v) FIELD_PREP(SWT_CR_HLK_MASK, (v)) |
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#define SWT_CR_ITR_MASK BIT(6) |
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#define SWT_CR_ITR(v) FIELD_PREP(SWT_CR_ITR_MASK, (v)) |
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#define SWT_CR_WND_MASK BIT(7) |
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#define SWT_CR_WND(v) FIELD_PREP(SWT_CR_WND_MASK, (v)) |
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#define SWT_CR_RIA_MASK BIT(8) |
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#define SWT_CR_RIA(v) FIELD_PREP(SWT_CR_RIA_MASK, (v)) |
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#define SWT_CR_SMD_MASK GENMASK(10, 9) |
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#define SWT_CR_SMD(v) FIELD_PREP(SWT_CR_SMD_MASK, (v)) |
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#define SWT_CR_MAP_MASK GENMASK(31, 24) |
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#define SWT_CR_MAP(v) FIELD_PREP(SWT_CR_MAP_MASK, (v)) |
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/* Interrupt */ |
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#define SWT_IR 0x4 |
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#define SWT_IR_TIF_MASK BIT(0) |
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#define SWT_IR_TIF(v) FIELD_PREP(SWT_IR_TIF_MASK, (v)) |
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/* Timeout */ |
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#define SWT_TO 0x8 |
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#define SWT_TO_WTO_MASK GENMASK(31, 0) |
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#define SWT_TO_WTO(v) FIELD_PREP(SWT_TO_WTO_MASK, (v)) |
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/* Window */ |
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#define SWT_WN 0xc |
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#define SWT_WN_WST_MASK GENMASK(31, 0) |
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#define SWT_WN_WST(v) FIELD_PREP(SWT_WN_WST_MASK, (v)) |
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/* Service */ |
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#define SWT_SR 0x10 |
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#define SWT_SR_WSC_MASK GENMASK(15, 0) |
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#define SWT_SR_WSC(v) FIELD_PREP(SWT_SR_WSC_MASK, (v)) |
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/* Counter Output */ |
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#define SWT_CO 0x14 |
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#define SWT_CO_CNT_MASK GENMASK(31, 0) |
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#define SWT_CO_CNT(v) FIELD_PREP(SWT_CO_CNT_MASK, (v)) |
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/* Service Key */ |
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#define SWT_SK 0x18 |
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#define SWT_SK_SK_MASK GENMASK(15, 0) |
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#define SWT_SK_SK(v) FIELD_PREP(SWT_SK_SK_MASK, (v)) |
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/* Event Request */ |
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#define SWT_RRR 0x1c |
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#define SWT_RRR_RRF_MASK BIT(0) |
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#define SWT_RRR_RRF(v) FIELD_PREP(SWT_RRR_RRF_MASK, (v)) |
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#define SWT_TO_WTO_MIN 0x100 |
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#define SWT_SR_WSC_UNLOCK_KEY1 0xC520U |
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#define SWT_SR_WSC_UNLOCK_KEY2 0xD928U |
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#define SWT_SR_WSC_SERVICE_KEY1 0xA602U |
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#define SWT_SR_WSC_SERVICE_KEY2 0xB480U |
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#define SWT_SOFT_LOCK_TIMEOUT_US 3000 |
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/* Handy accessors */ |
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#define REG_READ(r) sys_read32(config->base + (r)) |
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#define REG_WRITE(r, v) sys_write32((v), config->base + (r)) |
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enum swt_service_mode { |
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SWT_FIXED_SERVICE = 0, |
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SWT_KEYED_SERVICE = 1, |
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}; |
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enum swt_lock_mode { |
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SWT_UNLOCKED = 0, |
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SWT_SOFT_LOCK = 1, |
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SWT_HARD_LOCK = 2, |
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}; |
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struct swt_nxp_s32_timeout { |
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uint32_t period; |
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uint32_t window_start; |
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bool window_mode; |
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}; |
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struct swt_nxp_s32_config { |
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mem_addr_t base; |
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const struct device *clock_dev; |
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clock_control_subsys_t clock_subsys; |
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uint8_t master_access_mask; |
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enum swt_lock_mode lock_mode; |
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enum swt_service_mode service_mode; |
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uint16_t initial_key; |
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bool reset_on_invalid_access; |
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}; |
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struct swt_nxp_s32_data { |
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wdt_callback_t callback; |
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bool timeout_valid; |
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struct swt_nxp_s32_timeout timeout; |
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}; |
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static void swt_lock(const struct swt_nxp_s32_config *config) |
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{ |
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switch (config->lock_mode) { |
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case SWT_HARD_LOCK: |
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REG_WRITE(SWT_CR, REG_READ(SWT_CR) | SWT_CR_HLK(1U)); |
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break; |
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case SWT_SOFT_LOCK: |
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REG_WRITE(SWT_CR, REG_READ(SWT_CR) | SWT_CR_SLK(1U)); |
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break; |
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case SWT_UNLOCKED: |
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__fallthrough; |
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default: |
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break; |
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} |
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} |
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static int swt_unlock(const struct swt_nxp_s32_config *config) |
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{ |
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int err = 0; |
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if (FIELD_GET(SWT_CR_HLK_MASK, REG_READ(SWT_CR)) != 0U) { |
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LOG_ERR("Watchdog hard-locked"); |
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err = -EFAULT; |
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} else if (FIELD_GET(SWT_CR_SLK_MASK, REG_READ(SWT_CR)) != 0U) { |
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REG_WRITE(SWT_SR, SWT_SR_WSC(SWT_SR_WSC_UNLOCK_KEY1)); |
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REG_WRITE(SWT_SR, SWT_SR_WSC(SWT_SR_WSC_UNLOCK_KEY2)); |
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if (!WAIT_FOR(FIELD_GET(SWT_CR_SLK_MASK, REG_READ(SWT_CR) != 0), |
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SWT_SOFT_LOCK_TIMEOUT_US, NULL)) { |
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LOG_ERR("Timedout while trying to unlock"); |
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err = -ETIMEDOUT; |
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/* make sure is locked again before we leave */ |
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REG_WRITE(SWT_CR, REG_READ(SWT_CR) | SWT_CR_SLK(1U)); |
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} |
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} |
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return err; |
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} |
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static inline uint16_t swt_gen_service_key(const struct swt_nxp_s32_config *config) |
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{ |
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/* Calculated pseudo-random key according to Service Key Generation chapter in RM */ |
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return (uint16_t)((FIELD_GET(SWT_SK_SK_MASK, REG_READ(SWT_SK)) * 17U) + 3U); |
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} |
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static int swt_nxp_s32_setup(const struct device *dev, uint8_t options) |
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{ |
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const struct swt_nxp_s32_config *config = dev->config; |
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struct swt_nxp_s32_data *data = dev->data; |
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int err; |
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uint32_t reg_val; |
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if (!data->timeout_valid) { |
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LOG_ERR("No valid timeouts installed"); |
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return -EINVAL; |
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} |
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err = swt_unlock(config); |
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if (err) { |
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return err; |
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} |
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reg_val = REG_READ(SWT_CR); |
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reg_val &= ~(SWT_CR_WND_MASK | SWT_CR_STP_MASK | SWT_CR_FRZ_MASK | SWT_CR_ITR_MASK); |
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REG_WRITE(SWT_CR, reg_val | |
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SWT_CR_WND(data->timeout.window_mode ? 1U : 0U) | |
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SWT_CR_ITR(data->callback ? 1U : 0U) | |
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SWT_CR_STP((options & WDT_OPT_PAUSE_IN_SLEEP) ? 1U : 0U) | |
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SWT_CR_FRZ((options & WDT_OPT_PAUSE_HALTED_BY_DBG) ? 1U : 0U)); |
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REG_WRITE(SWT_IR, SWT_IR_TIF(1U)); |
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REG_WRITE(SWT_TO, SWT_TO_WTO(data->timeout.period)); |
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REG_WRITE(SWT_WN, SWT_WN_WST(data->timeout.window_start)); |
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if (config->service_mode == SWT_KEYED_SERVICE) { |
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REG_WRITE(SWT_SK, SWT_SK_SK(config->initial_key)); |
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} |
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REG_WRITE(SWT_CR, REG_READ(SWT_CR) | SWT_CR_WEN(1U)); |
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swt_lock(config); |
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return 0; |
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} |
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static int swt_nxp_s32_disable(const struct device *dev) |
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{ |
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const struct swt_nxp_s32_config *config = dev->config; |
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struct swt_nxp_s32_data *data = dev->data; |
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int err; |
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if (!FIELD_GET(SWT_CR_WEN_MASK, REG_READ(SWT_CR))) { |
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LOG_ERR("Watchdog is not enabled"); |
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return -EFAULT; |
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} |
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err = swt_unlock(config); |
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if (err) { |
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return err; |
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} |
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/* Disable the watchdog and clear interrupt flags */ |
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REG_WRITE(SWT_CR, REG_READ(SWT_CR) & ~SWT_CR_WEN_MASK); |
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REG_WRITE(SWT_IR, SWT_IR_TIF(1U)); |
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swt_lock(config); |
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data->timeout_valid = false; |
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return 0; |
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} |
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static int swt_nxp_s32_install_timeout(const struct device *dev, |
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const struct wdt_timeout_cfg *cfg) |
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{ |
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const struct swt_nxp_s32_config *config = dev->config; |
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struct swt_nxp_s32_data *data = dev->data; |
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bool window_mode = false; |
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uint32_t window = 0; |
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uint32_t period; |
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uint32_t clock_rate; |
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int err; |
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if (data->timeout_valid) { |
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LOG_ERR("No more timeouts can be installed"); |
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return -ENOMEM; |
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} |
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err = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate); |
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if (err) { |
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LOG_ERR("Failed to get module clock frequency"); |
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return err; |
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} |
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period = clock_rate / 1000U * cfg->window.max; |
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if (cfg->window.min) { |
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window_mode = true; |
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window = clock_rate / 1000U * (cfg->window.max - cfg->window.min); |
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} |
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if ((period < SWT_TO_WTO_MIN) || (period < window)) { |
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LOG_ERR("Invalid timeout"); |
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return -EINVAL; |
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} |
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data->timeout.period = period; |
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data->timeout.window_start = window; |
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data->timeout.window_mode = window_mode; |
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data->callback = cfg->callback; |
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data->timeout_valid = true; |
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LOG_DBG("Installed timeout: period=%d, window=%d (%s)", |
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period, window, window_mode ? "enabled" : "disabled"); |
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return 0; |
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} |
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static int swt_nxp_s32_feed(const struct device *dev, int channel) |
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{ |
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const struct swt_nxp_s32_config *config = dev->config; |
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bool match_unlock_seq = false; |
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int err = 0; |
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ARG_UNUSED(channel); |
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switch (config->service_mode) { |
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case SWT_FIXED_SERVICE: |
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REG_WRITE(SWT_SR, SWT_SR_WSC(SWT_SR_WSC_SERVICE_KEY1)); |
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REG_WRITE(SWT_SR, SWT_SR_WSC(SWT_SR_WSC_SERVICE_KEY2)); |
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break; |
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case SWT_KEYED_SERVICE: |
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/* |
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* If one or more service routines use both unlock keys in the proper order, |
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* the watchdog unlocks the soft lock |
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*/ |
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if (swt_gen_service_key(config) == SWT_SR_WSC_UNLOCK_KEY1) { |
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match_unlock_seq = true; |
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} |
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REG_WRITE(SWT_SR, SWT_SR_WSC(swt_gen_service_key(config))); |
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if (swt_gen_service_key(config) == SWT_SR_WSC_UNLOCK_KEY1) { |
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match_unlock_seq = true; |
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} |
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REG_WRITE(SWT_SR, SWT_SR_WSC(swt_gen_service_key(config))); |
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if (match_unlock_seq && (config->lock_mode == SWT_SOFT_LOCK)) { |
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/* |
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* Service key generated matched the unlock sequence, complete the |
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* unlock sequence and reinitiate the soft lock |
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*/ |
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REG_WRITE(SWT_SR, SWT_SR_WSC(SWT_SR_WSC_UNLOCK_KEY2)); |
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swt_lock(config); |
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} |
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break; |
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default: |
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LOG_ERR("Invalid service mode"); |
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err = -EINVAL; |
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break; |
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} |
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LOG_DBG("Fed the watchdog"); |
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return err; |
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} |
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static void swt_nxp_s32_isr(const struct device *dev) |
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{ |
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const struct swt_nxp_s32_config *config = dev->config; |
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struct swt_nxp_s32_data *data = dev->data; |
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uint32_t reg_val; |
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if (FIELD_GET(SWT_IR_TIF_MASK, REG_READ(SWT_IR)) && |
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FIELD_GET(SWT_CR_ITR_MASK, REG_READ(SWT_CR))) { |
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/* Clear interrupt flag */ |
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reg_val = REG_READ(SWT_IR); |
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reg_val &= SWT_IR_TIF_MASK; |
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REG_WRITE(SWT_IR, reg_val); |
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if (data->callback) { |
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/* SWT only has one channel */ |
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data->callback(dev, 0U); |
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} |
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} |
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} |
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static int swt_nxp_s32_init(const struct device *dev) |
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{ |
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const struct swt_nxp_s32_config *config = dev->config; |
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int err; |
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if (!device_is_ready(config->clock_dev)) { |
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return -ENODEV; |
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} |
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err = clock_control_on(config->clock_dev, config->clock_subsys); |
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if (err) { |
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return err; |
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} |
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REG_WRITE(SWT_CR, |
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SWT_CR_MAP(config->master_access_mask) | |
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SWT_CR_RIA(config->reset_on_invalid_access) | |
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SWT_CR_SMD(config->service_mode)); |
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return 0; |
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} |
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static DEVICE_API(wdt, swt_nxp_s32_driver_api) = { |
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.setup = swt_nxp_s32_setup, |
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.disable = swt_nxp_s32_disable, |
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.install_timeout = swt_nxp_s32_install_timeout, |
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.feed = swt_nxp_s32_feed, |
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}; |
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#define SWT_NXP_S32_DEVICE_INIT(n) \ |
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static struct swt_nxp_s32_data swt_nxp_s32_data_##n; \ |
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\ |
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static const struct swt_nxp_s32_config swt_nxp_s32_config_##n = { \ |
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.base = DT_INST_REG_ADDR(n), \ |
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ |
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.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name), \ |
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.master_access_mask = DT_INST_PROP(n, master_access_mask), \ |
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.reset_on_invalid_access = DT_INST_PROP(n, reset_on_invalid_access), \ |
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.service_mode = DT_INST_ENUM_IDX(n, service_mode), \ |
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.initial_key = (uint16_t)DT_INST_PROP(n, initial_key), \ |
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.lock_mode = DT_INST_ENUM_IDX(n, lock_mode), \ |
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}; \ |
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\ |
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static int swt_nxp_s32_##n##_init(const struct device *dev) \ |
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{ \ |
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int err; \ |
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\ |
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err = swt_nxp_s32_init(dev); \ |
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if (err) { \ |
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return err; \ |
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} \ |
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\ |
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \ |
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swt_nxp_s32_isr, DEVICE_DT_INST_GET(n), \ |
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COND_CODE_1(DT_INST_IRQ_HAS_CELL(n, flags), \ |
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(DT_INST_IRQ(n, flags)), (0))); \ |
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irq_enable(DT_INST_IRQN(n)); \ |
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\ |
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return 0; \ |
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} \ |
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\ |
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DEVICE_DT_INST_DEFINE(n, \ |
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swt_nxp_s32_##n##_init, \ |
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NULL, \ |
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&swt_nxp_s32_data_##n, \ |
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&swt_nxp_s32_config_##n, \ |
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POST_KERNEL, \ |
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \ |
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&swt_nxp_s32_driver_api); |
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DT_INST_FOREACH_STATUS_OKAY(SWT_NXP_S32_DEVICE_INIT)
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