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101 lines
2.8 KiB
101 lines
2.8 KiB
/* |
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* Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io> |
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* Copyright (c) 2018 Xilinx, Inc. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#ifndef ZEPHYR_DRIVERS_TIMER_XLNX_PSTTC_TIMER_PRIV_H_ |
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#define ZEPHYR_DRIVERS_TIMER_XLNX_PSTTC_TIMER_PRIV_H_ |
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/* |
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* Refer to the "Zynq UltraScale+ Device Technical Reference Manual" document |
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* from Xilinx for more information on this peripheral. |
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*/ |
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/* |
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* Triple-timer Counter (TTC) Register Offsets |
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*/ |
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/* Clock Control Register */ |
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#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U |
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/* Counter Control Register*/ |
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#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU |
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/* Current Counter Value */ |
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#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U |
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/* Interval Count Value */ |
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#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U |
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/* Match 1 value */ |
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#define XTTCPS_MATCH_0_OFFSET 0x00000030U |
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/* Match 2 value */ |
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#define XTTCPS_MATCH_1_OFFSET 0x0000003CU |
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/* Match 3 value */ |
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#define XTTCPS_MATCH_2_OFFSET 0x00000048U |
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/* Interrupt Status Register */ |
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#define XTTCPS_ISR_OFFSET 0x00000054U |
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/* Interrupt Enable Register */ |
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#define XTTCPS_IER_OFFSET 0x00000060U |
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/* |
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* Clock Control Register Definitions |
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*/ |
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/* Prescale enable */ |
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#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U |
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/* Prescale value */ |
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#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU |
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/* Prescale shift */ |
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#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U |
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/* Prescale disable */ |
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#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U |
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/* Clock source */ |
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#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U |
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/* External Clock edge */ |
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#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U |
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/* |
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* Counter Control Register Definitions |
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*/ |
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/* Disable the counter */ |
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#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U |
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/* Interval mode */ |
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#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U |
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/* Decrement mode */ |
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#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U |
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/* Match mode */ |
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#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U |
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/* Reset counter */ |
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#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U |
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/* Enable waveform */ |
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#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U |
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/* Waveform polarity */ |
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#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U |
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/* Reset value */ |
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#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U |
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/* |
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* Interrupt Register Definitions |
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*/ |
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/* Interval Interrupt */ |
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#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U |
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/* Match 1 Interrupt */ |
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#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U |
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/* Match 2 Interrupt */ |
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#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U |
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/* Match 3 Interrupt */ |
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#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U |
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/* Counter Overflow */ |
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#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U |
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/* All valid Interrupts */ |
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#define XTTCPS_IXR_ALL_MASK 0x0000001FU |
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/* |
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* Constants |
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*/ |
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/* Maximum value of interval counter */ |
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#define XTTC_MAX_INTERVAL_COUNT 0xFFFFFFFFU |
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#endif /* ZEPHYR_DRIVERS_TIMER_XLNX_PSTTC_TIMER_PRIV_H_ */
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