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117 lines
3.1 KiB
117 lines
3.1 KiB
/* |
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* Copyright (c) 2019 Intel Corporation |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <zephyr/init.h> |
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#include <zephyr/drivers/timer/system_timer.h> |
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#include <zephyr/sys_clock.h> |
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#include <zephyr/spinlock.h> |
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#include <zephyr/drivers/interrupt_controller/loapic.h> |
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#include <zephyr/irq.h> |
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BUILD_ASSERT(!IS_ENABLED(CONFIG_TICKLESS_KERNEL), "this is a tickfull driver"); |
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/* |
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* Overview: |
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* |
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* This driver enables the local APIC as the Zephyr system timer. It supports |
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* legacy ("tickful") mode only. The driver will work with any APIC that has |
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* the ARAT "always running APIC timer" feature (CPUID 0x06, EAX bit 2). |
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* |
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* Configuration: |
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* |
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* CONFIG_APIC_TIMER=y enables this timer driver. |
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* CONFIG_APIC_TIMER_IRQ=<irq> which IRQ to configure for the timer. |
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* CONFIG_APIC_TIMER_IRQ_PRIORITY=<p> priority for IRQ_CONNECT() |
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* |
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* CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=<hz> must contain the frequency seen |
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* by the local APIC timer block (before it gets to the timer divider). |
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*/ |
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/* These should be merged into include/drivers/interrupt_controller/loapic.h. */ |
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#define DCR_DIVIDER_MASK 0x0000000F /* divider bits */ |
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#define DCR_DIVIDER 0x0000000B /* divide by 1 */ |
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#define LVT_MODE_MASK 0x00060000 /* timer mode bits */ |
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#define LVT_MODE 0x00020000 /* periodic mode */ |
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#if defined(CONFIG_TEST) |
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const int32_t z_sys_timer_irq_for_test = CONFIG_APIC_TIMER_IRQ; |
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#endif |
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#define CYCLES_PER_TICK \ |
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(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC) |
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BUILD_ASSERT(CYCLES_PER_TICK >= 1, "APIC timer: bad CYCLES_PER_TICK"); |
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static volatile uint64_t total_cycles; |
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static void isr(const void *arg) |
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{ |
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ARG_UNUSED(arg); |
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total_cycles += CYCLES_PER_TICK; |
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sys_clock_announce(1); |
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} |
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uint32_t sys_clock_elapsed(void) |
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{ |
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return 0U; |
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} |
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uint64_t sys_clock_cycle_get_64(void) |
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{ |
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uint32_t ccr_1st, ccr_2nd; |
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uint64_t cycles; |
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/* |
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* We may race with CCR reaching 0 and reloading, and the interrupt |
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* handler updating total_cycles. Let's make sure we sample everything |
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* away from this roll-over transition by ensuring consecutive CCR |
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* values are descending so we're sure the enclosed (volatile) |
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* total_cycles sample and CCR value are coherent with each other. |
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*/ |
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do { |
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ccr_1st = x86_read_loapic(LOAPIC_TIMER_CCR); |
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cycles = total_cycles; |
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ccr_2nd = x86_read_loapic(LOAPIC_TIMER_CCR); |
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} while (ccr_2nd > ccr_1st); |
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return cycles + (CYCLES_PER_TICK - ccr_2nd); |
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} |
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uint32_t sys_clock_cycle_get_32(void) |
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{ |
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return (uint32_t)sys_clock_cycle_get_64(); |
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} |
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static int sys_clock_driver_init(void) |
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{ |
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uint32_t val; |
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val = x86_read_loapic(LOAPIC_TIMER_CONFIG); /* set divider */ |
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val &= ~DCR_DIVIDER_MASK; |
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val |= DCR_DIVIDER; |
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x86_write_loapic(LOAPIC_TIMER_CONFIG, val); |
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val = x86_read_loapic(LOAPIC_TIMER); /* set timer mode */ |
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val &= ~LVT_MODE_MASK; |
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val |= LVT_MODE; |
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x86_write_loapic(LOAPIC_TIMER, val); |
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/* remember, wiring up the interrupt will mess with the LVT, too */ |
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IRQ_CONNECT(CONFIG_APIC_TIMER_IRQ, |
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CONFIG_APIC_TIMER_IRQ_PRIORITY, |
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isr, 0, 0); |
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x86_write_loapic(LOAPIC_TIMER_ICR, CYCLES_PER_TICK); |
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irq_enable(CONFIG_APIC_TIMER_IRQ); |
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return 0; |
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} |
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SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2, |
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CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
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