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129 lines
3.0 KiB
129 lines
3.0 KiB
/* |
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* Copyright (c) 2023 Intel Corporation. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT intel_blinky_pwm |
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#include <errno.h> |
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#include <soc.h> |
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#include <zephyr/device.h> |
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#include <zephyr/kernel.h> |
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#include <zephyr/init.h> |
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#include <zephyr/sys/util.h> |
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#include <zephyr/devicetree.h> |
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#include <zephyr/drivers/pwm.h> |
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#define PWM_ENABLE 0x80000000 |
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#define PWM_SWUP 0x40000000 |
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#define PWM_FREQ_INT_SHIFT 8 |
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#define PWM_BASE_UNIT_FRACTION 14 |
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#define PWM_FREQ_MAX 0x100 |
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#define PWM_DUTY_MAX 0x100 |
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struct bk_intel_config { |
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DEVICE_MMIO_NAMED_ROM(reg_base); |
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uint32_t reg_offset; |
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uint32_t clock_freq; |
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uint32_t max_pins; |
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}; |
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struct bk_intel_runtime { |
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DEVICE_MMIO_NAMED_RAM(reg_base); |
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}; |
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static int bk_intel_set_cycles(const struct device *dev, uint32_t pin, |
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uint32_t period_cycles, uint32_t pulse_cycles, |
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pwm_flags_t flags) |
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{ |
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struct bk_intel_runtime *rt = dev->data; |
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const struct bk_intel_config *cfg = dev->config; |
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uint32_t ret = 0; |
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uint32_t val = 0; |
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uint32_t duty; |
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float period; |
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float out_freq; |
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uint32_t base_unit; |
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if (pin >= cfg->max_pins) { |
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ret = -EINVAL; |
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goto err; |
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} |
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out_freq = cfg->clock_freq / (float) period_cycles; |
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period = (out_freq * PWM_FREQ_MAX) / cfg->clock_freq; |
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base_unit = (uint32_t) (period * (1 << PWM_BASE_UNIT_FRACTION)); |
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duty = (pulse_cycles * PWM_DUTY_MAX) / period_cycles; |
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if (duty) { |
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val = PWM_DUTY_MAX - duty; |
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val |= (base_unit << PWM_FREQ_INT_SHIFT); |
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} else { |
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val = PWM_DUTY_MAX - 1; |
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} |
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val |= PWM_ENABLE | PWM_SWUP; |
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if (period >= PWM_FREQ_MAX) { |
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ret = -EINVAL; |
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goto err; |
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} |
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if (duty > PWM_DUTY_MAX) { |
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ret = -EINVAL; |
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goto err; |
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} |
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sys_write32(val, rt->reg_base + cfg->reg_offset); |
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err: |
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return ret; |
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} |
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static int bk_intel_get_cycles_per_sec(const struct device *dev, uint32_t pin, |
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uint64_t *cycles) |
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{ |
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const struct bk_intel_config *cfg = dev->config; |
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if (pin >= cfg->max_pins) { |
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return -EINVAL; |
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} |
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*cycles = cfg->clock_freq; |
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return 0; |
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} |
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static DEVICE_API(pwm, api_funcs) = { |
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.set_cycles = bk_intel_set_cycles, |
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.get_cycles_per_sec = bk_intel_get_cycles_per_sec, |
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}; |
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static int bk_intel_init(const struct device *dev) |
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{ |
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struct bk_intel_runtime *runtime = dev->data; |
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const struct bk_intel_config *config = dev->config; |
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device_map(&runtime->reg_base, |
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config->reg_base.phys_addr & ~0xFFU, |
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config->reg_base.size, |
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K_MEM_CACHE_NONE); |
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return 0; |
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} |
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#define BK_INTEL_DEV_CFG(n) \ |
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static const struct bk_intel_config bk_cfg_##n = { \ |
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DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \ |
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.reg_offset = DT_INST_PROP(n, reg_offset), \ |
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.max_pins = DT_INST_PROP(n, max_pins), \ |
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.clock_freq = DT_INST_PROP(n, clock_frequency), \ |
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}; \ |
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\ |
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static struct bk_intel_runtime bk_rt_##n; \ |
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DEVICE_DT_INST_DEFINE(n, &bk_intel_init, NULL, \ |
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&bk_rt_##n, &bk_cfg_##n, \ |
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \ |
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&api_funcs); \ |
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DT_INST_FOREACH_STATUS_OKAY(BK_INTEL_DEV_CFG)
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