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122 lines
4.3 KiB
122 lines
4.3 KiB
/* Copyright (c) 2025 Silicon Laboratories Inc. |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT silabs_siwx91x_qspi_memory |
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#include <zephyr/logging/log.h> |
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#include <zephyr/drivers/clock_control.h> |
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#include <zephyr/drivers/pinctrl.h> |
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#include <zephyr/sys/util.h> |
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#include <zephyr/device.h> |
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#include <zephyr/kernel.h> |
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#include "rsi_qspi_proto.h" |
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#include "sl_si91x_psram_handle.h" |
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LOG_MODULE_REGISTER(siwx91x_memc, CONFIG_MEMC_LOG_LEVEL); |
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struct siwx91x_memc_config { |
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qspi_reg_t *reg; |
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const struct device *clock_dev; |
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clock_control_subsys_t clock_subsys; |
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const struct pinctrl_dev_config *pincfg; |
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}; |
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static int siwx91x_memc_init(const struct device *dev) |
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{ |
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const struct siwx91x_memc_config *config = dev->config; |
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int ret; |
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/* Memory controller is automatically setup by the siwx91x bootloader, |
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* so we have to uninitialize it before to change the configuration |
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*/ |
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ret = sl_si91x_psram_uninit(); |
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if (ret) { |
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return -EIO; |
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} |
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ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); |
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if (ret) { |
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return -EIO; |
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} |
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if (config->clock_dev) { |
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ret = device_is_ready(config->clock_dev); |
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if (!ret) { |
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return -EINVAL; |
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} |
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ret = clock_control_on(config->clock_dev, config->clock_subsys); |
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if (ret && ret != -EALREADY && ret != -ENOSYS) { |
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return ret; |
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} |
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} |
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ret = sl_si91x_psram_init(); |
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if (ret) { |
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LOG_ERR("sl_si91x_psram_init() returned %d", ret); |
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return -EIO; |
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} |
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return 0; |
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} |
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PINCTRL_DT_INST_DEFINE(0); |
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static const struct siwx91x_memc_config siwx91x_memc_config = { |
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.reg = (void *)DT_INST_REG_ADDR(0), |
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.clock_dev = DEVICE_DT_GET_OR_NULL(DT_INST_CLOCKS_CTLR(0)), |
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.clock_subsys = (void *)DT_INST_PHA_OR(0, clocks, clkid, NULL), |
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.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0), |
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}; |
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/* Required to properly initialize ,deviceID */ |
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static const uint8_t devid[] = DT_INST_PROP(0, device_id); |
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/* PSRAM_Device is directly referenced by sl_si91x_psram_init() */ |
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struct sl_psram_info_type_t PSRAM_Device = { |
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.deviceID.MFID = devid[0], |
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.deviceID.KGD = devid[1], |
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.deviceID.EID = { devid[2], devid[3], devid[4], devid[5], devid[6], devid[7] }, |
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/* FIXME: Currently, the Chip Select (.cs_no property) and the RAM start |
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* address are hard coded. The hardware also support Chip Select == 1, |
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* then RAM start address will be 0xb000000. |
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*/ |
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.devDensity = DT_REG_SIZE(DT_INST_CHILD(0, psram_a000000)), |
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.normalReadMAXFrequency = DT_INST_PROP(0, normal_freq), |
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.fastReadMAXFrequency = DT_INST_PROP(0, fast_freq), |
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.rwType = QUAD_RW, |
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.defaultBurstWrapSize = 1024, |
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.toggleBurstWrapSize = 0, |
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.spi_config.spi_config_2.auto_mode = 1, |
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/* FIXME: user may want to customize these values */ |
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.spi_config.spi_config_1.read_cmd = 0xEB, |
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.spi_config.spi_config_3.wr_cmd = 0x38, |
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.spi_config.spi_config_1.extra_byte_mode = QUAD_MODE, |
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.spi_config.spi_config_1.dummy_mode = QUAD_MODE, |
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.spi_config.spi_config_1.addr_mode = QUAD_MODE, |
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.spi_config.spi_config_1.data_mode = QUAD_MODE, |
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.spi_config.spi_config_1.inst_mode = QUAD_MODE, |
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.spi_config.spi_config_3.wr_addr_mode = QUAD_MODE, |
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.spi_config.spi_config_3.wr_data_mode = QUAD_MODE, |
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.spi_config.spi_config_3.wr_inst_mode = QUAD_MODE, |
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.spi_config.spi_config_2.wrap_len_in_bytes = NO_WRAP, |
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.spi_config.spi_config_2.swap_en = 1, |
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.spi_config.spi_config_2.addr_width = 3, /* 24 bits */ |
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.spi_config.spi_config_2.cs_no = 0, |
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.spi_config.spi_config_4.secondary_csn = 1, |
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.spi_config.spi_config_2.neg_edge_sampling = 1, |
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.spi_config.spi_config_1.no_of_dummy_bytes = 3, |
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.spi_config.spi_config_1.dummy_W_or_R = DUMMY_READS, |
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.spi_config.spi_config_2.full_duplex = IGNORE_FULL_DUPLEX, |
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.spi_config.spi_config_2.qspi_clk_en = QSPI_FULL_TIME_CLK, |
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.spi_config.spi_config_1.flash_type = 0xf, |
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.spi_config.spi_config_3.dummys_4_jump = 1, |
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.spi_config.spi_config_4.valid_prot_bits = 4, |
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.spi_config.spi_config_1.d3d2_data = 0x03, |
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.spi_config.spi_config_5.d7_d4_data = 0x0f, |
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}; |
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/* PSRAMSecureSegments is directly referenced by sl_si91x_psram_init() */ |
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struct PSRAMSecureSegmentType PSRAMSecureSegments[MAX_SEC_SEGMENTS] = { |
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[0].segmentEnable = 1, |
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[0].lowerBoundary = 0x00000, |
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[0].higherBoundary = 0x0ffff, |
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}; |
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DEVICE_DT_INST_DEFINE(0, siwx91x_memc_init, NULL, NULL, &siwx91x_memc_config, |
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PRE_KERNEL_1, CONFIG_MEMC_INIT_PRIORITY, NULL);
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