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218 lines
7.4 KiB
218 lines
7.4 KiB
/* |
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* Copyright (c) 2023 Intel Corporation. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT snps_dwcxgmac_mdio |
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#include <errno.h> |
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#include <zephyr/kernel.h> |
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#include <zephyr/device.h> |
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#include <zephyr/drivers/mdio.h> |
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#include <zephyr/init.h> |
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#include <zephyr/logging/log.h> |
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#include <zephyr/drivers/reset.h> |
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LOG_MODULE_REGISTER(snps_dwcxgmac_mdio, CONFIG_MDIO_LOG_LEVEL); |
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#define XGMAC_DMA_BASE_ADDR_OFFSET (0x3000u) |
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#define DMA_MODE_OFST (0x0) |
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#define DMA_MODE_SWR_SET_MSK (0x00000001) |
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#define DMA_MODE_SWR_SET(value) ((value) & 0x00000001) |
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#define MDIO_READ_CMD (3u) |
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#define MDIO_WRITE_CMD (1u) |
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#define CORE_MDIO_SINGLE_COMMAND_ADDRESS_OFST 0x200 |
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#define CORE_MDIO_SINGLE_COMMAND_ADDRESS_RA_SET(value) (((value) << 0) & 0x0000ffff) |
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#define CORE_MDIO_SINGLE_COMMAND_ADDRESS_PA_SET(value) (((value) << 16) & 0x001f0000) |
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#define CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_OFST 0x204 |
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#define CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_SBUSY_SET_MSK BIT(22) |
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#define CORE_MDIO_CLAUSE_22_PORT_OFST 0x220 |
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#define CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_SDATA_SET(value) (((value) << 0) & 0x0000ffff) |
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#define CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_CMD_SET(value) (((value) << 16) & 0x00030000) |
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#define CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_SADDR_SET(value) (((value) << 18) & 0x00040000) |
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#define CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_CR_SET(value) (((value) << 19) & 0x00380000) |
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#define CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_CRS_SET(value) (((value) << 31) & 0x80000000) |
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#define CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_SBUSY_SET(value) (((value) << 22) & 0x00400000) |
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#define CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_SDATA_GET(value) (((value) & 0x0000ffff) >> 0) |
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struct mdio_dwcxgmac_dev_data { |
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DEVICE_MMIO_RAM; |
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struct k_mutex mdio_transfer_lock; |
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}; |
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struct mdio_dwcxgmac_dev_config { |
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DEVICE_MMIO_ROM; |
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uint32_t clk_range; |
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bool clk_range_sel; |
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#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(resets) |
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/* XGMAC peripheral reset signal */ |
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const struct reset_dt_spec reset; |
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#endif |
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}; |
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static inline int dwxgmac_software_reset(mem_addr_t ioaddr) |
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{ |
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uint32_t delay_us = CONFIG_MDIO_DWCXGMAC_STATUS_BUSY_CHECK_TIMEOUT; |
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bool ret; |
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/* software reset */ |
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mem_addr_t reg_addr = (mem_addr_t)(ioaddr + XGMAC_DMA_BASE_ADDR_OFFSET + DMA_MODE_OFST); |
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sys_write32(DMA_MODE_SWR_SET(1u), reg_addr); |
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ret = WAIT_FOR(!(sys_read32(reg_addr) & DMA_MODE_SWR_SET_MSK), delay_us, k_msleep(1)); |
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if (ret == false) { |
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return -ETIMEDOUT; |
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} |
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return 0; |
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} |
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static inline int mdio_busy_wait(uint32_t reg_addr, uint32_t bit_msk) |
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{ |
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uint32_t delay_us = CONFIG_MDIO_DWCXGMAC_STATUS_BUSY_CHECK_TIMEOUT; |
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bool ret; |
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ret = WAIT_FOR(!(sys_read32(reg_addr) & bit_msk), delay_us, k_msleep(1)); |
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if (ret == false) { |
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return -ETIMEDOUT; |
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} |
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return 0; |
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} |
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static int mdio_transfer(const struct device *dev, uint8_t prtad, uint8_t devad, uint8_t rw, |
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uint16_t data_in, uint16_t *data_out) |
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{ |
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const struct mdio_dwcxgmac_dev_config *const cfg = |
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(struct mdio_dwcxgmac_dev_config *)dev->config; |
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struct mdio_dwcxgmac_dev_data *const data = (struct mdio_dwcxgmac_dev_data *)dev->data; |
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int retval; |
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mem_addr_t ioaddr = 0; |
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uint32_t reg_addr; |
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uint32_t reg_data, mdio_addr, mdio_data = 0; |
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ioaddr = (mem_addr_t)DEVICE_MMIO_GET(dev); |
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retval = mdio_busy_wait((ioaddr + CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_OFST), |
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CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_SBUSY_SET_MSK); |
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if (retval) { |
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LOG_ERR("%s: MDIO device busy wait timedout", dev->name); |
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return retval; |
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} |
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(void)k_mutex_lock(&data->mdio_transfer_lock, K_FOREVER); |
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/* Set port as Clause 22 */ |
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reg_addr = ioaddr + CORE_MDIO_CLAUSE_22_PORT_OFST; |
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reg_data = sys_read32(reg_addr); |
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reg_data |= BIT(prtad); |
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sys_write32(reg_data, reg_addr); |
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reg_addr = ioaddr + CORE_MDIO_SINGLE_COMMAND_ADDRESS_OFST; |
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mdio_addr = CORE_MDIO_SINGLE_COMMAND_ADDRESS_RA_SET(devad) | |
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CORE_MDIO_SINGLE_COMMAND_ADDRESS_PA_SET(prtad); |
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sys_write32(mdio_addr, reg_addr); |
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reg_addr = ioaddr + CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_OFST; |
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mdio_data = CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_SDATA_SET(data_in) | |
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CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_CMD_SET(rw) | |
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CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_SADDR_SET(1u) | |
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CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_CR_SET(cfg->clk_range) | |
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CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_CRS_SET(cfg->clk_range_sel) | |
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CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_SBUSY_SET(1u); |
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sys_write32(mdio_data, reg_addr); |
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retval = mdio_busy_wait(reg_addr, CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_SBUSY_SET_MSK); |
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if (retval) { |
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LOG_ERR("%s: transfer timedout", dev->name); |
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} else { |
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if (data_out) { |
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*data_out = CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_SDATA_GET( |
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sys_read32(reg_addr)); |
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} |
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} |
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(void)k_mutex_unlock(&data->mdio_transfer_lock); |
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return retval; |
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} |
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static int mdio_dwcxgmac_read(const struct device *dev, uint8_t prtad, uint8_t regad, |
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uint16_t *data) |
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{ |
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return mdio_transfer(dev, prtad, regad, MDIO_READ_CMD, 0, data); |
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} |
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static int mdio_dwcxgmac_write(const struct device *dev, uint8_t prtad, uint8_t regad, |
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uint16_t data) |
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{ |
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return mdio_transfer(dev, prtad, regad, MDIO_WRITE_CMD, data, NULL); |
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} |
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static int mdio_dwcxgmac_initialize(const struct device *dev) |
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{ |
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struct mdio_dwcxgmac_dev_data *const data = (struct mdio_dwcxgmac_dev_data *)dev->data; |
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const struct mdio_dwcxgmac_dev_config *const cfg = |
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(struct mdio_dwcxgmac_dev_config *)dev->config; |
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mem_addr_t ioaddr; |
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int ret = 0; |
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#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(resets) |
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if (cfg->reset.dev != NULL) { |
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if (!device_is_ready(cfg->reset.dev)) { |
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LOG_ERR("%s, Reset device is not ready", dev->name); |
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return -ENODEV; |
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} |
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ret = reset_line_toggle(cfg->reset.dev, cfg->reset.id); |
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if (ret) { |
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LOG_ERR("%s: Failed to reset peripheral", dev->name); |
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return ret; |
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} |
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} else { |
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LOG_ERR("%s, Reset device is not available", dev->name); |
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return -ENODEV; |
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} |
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#endif |
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DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE); |
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ioaddr = (mem_addr_t)DEVICE_MMIO_GET(dev); |
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ret = dwxgmac_software_reset(ioaddr); |
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if (ret) { |
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LOG_ERR("%s: XGMAC reset timeout", dev->name); |
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return ret; |
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} |
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k_mutex_init(&data->mdio_transfer_lock); |
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return 0; |
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} |
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static DEVICE_API(mdio, mdio_dwcxgmac_driver_api) = { |
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.read = mdio_dwcxgmac_read, |
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.write = mdio_dwcxgmac_write, |
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}; |
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#define XGMAC_SNPS_DESIGNWARE_RESET_SPEC_INIT(n) .reset = RESET_DT_SPEC_INST_GET(n), |
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#define MDIO_DWCXGMAC_CONFIG(n) \ |
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static const struct mdio_dwcxgmac_dev_config mdio_dwcxgmac_dev_config_##n = { \ |
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DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)), \ |
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.clk_range = DT_INST_PROP(n, csr_clock_indx), \ |
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.clk_range_sel = DT_INST_PROP(n, clock_range_sel), \ |
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IF_ENABLED(DT_INST_NODE_HAS_PROP(n, resets), \ |
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(XGMAC_SNPS_DESIGNWARE_RESET_SPEC_INIT(n)))}; |
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#define MDIO_DWCXGMAC_DEVICE(n) \ |
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MDIO_DWCXGMAC_CONFIG(n); \ |
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static struct mdio_dwcxgmac_dev_data mdio_dwcxgmac_dev_data##n; \ |
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DEVICE_DT_INST_DEFINE(n, &mdio_dwcxgmac_initialize, NULL, &mdio_dwcxgmac_dev_data##n, \ |
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&mdio_dwcxgmac_dev_config_##n, POST_KERNEL, \ |
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CONFIG_MDIO_INIT_PRIORITY, &mdio_dwcxgmac_driver_api); |
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DT_INST_FOREACH_STATUS_OKAY(MDIO_DWCXGMAC_DEVICE)
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