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262 lines
9.8 KiB
262 lines
9.8 KiB
/* |
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* Copyright 2022-2024 NXP |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT nxp_s32_siul2_eirq |
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#include <soc.h> |
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#include <zephyr/irq.h> |
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#include <zephyr/sys/sys_io.h> |
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#include <zephyr/sys/math_extras.h> |
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#include <zephyr/drivers/pinctrl.h> |
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#include <zephyr/drivers/interrupt_controller/intc_eirq_nxp_s32.h> |
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/* SIUL2 External Interrupt Controller registers (offsets from DISR0) */ |
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/* SIUL2 DMA/Interrupt Status Flag */ |
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#define SIUL2_DISR0 0x0 |
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/* SIUL2 DMA/Interrupt Request Enable */ |
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#define SIUL2_DIRER0 0x8 |
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/* SIUL2 DMA/Interrupt Request Select */ |
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#define SIUL2_DIRSR0 0x10 |
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/* SIUL2 Interrupt Rising-Edge Event Enable */ |
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#define SIUL2_IREER0 0x18 |
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/* SIUL2 Interrupt Falling-Edge Event Enable */ |
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#define SIUL2_IFEER0 0x20 |
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/* SIUL2 Interrupt Filter Enable */ |
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#define SIUL2_IFER0 0x28 |
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/* SIUL2 Interrupt Filter Maximum Counter Register */ |
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#define SIUL2_IFMCR(n) (0x30 + 0x4 * (n)) |
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#define SIUL2_IFMCR_MAXCNT_MASK GENMASK(3, 0) |
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#define SIUL2_IFMCR_MAXCNT(v) FIELD_PREP(SIUL2_IFMCR_MAXCNT_MASK, (v)) |
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/* SIUL2 Interrupt Filter Clock Prescaler Register */ |
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#define SIUL2_IFCPR 0xb0 |
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#define SIUL2_IFCPR_IFCP_MASK GENMASK(3, 0) |
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#define SIUL2_IFCPR_IFCP(v) FIELD_PREP(SIUL2_IFCPR_IFCP_MASK, (v)) |
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/* Handy accessors */ |
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#define REG_READ(r) sys_read32(config->base + (r)) |
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#define REG_WRITE(r, v) sys_write32((v), config->base + (r)) |
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#define GLITCH_FILTER_DISABLED (SIUL2_IFMCR_MAXCNT_MASK + 1) |
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struct eirq_nxp_s32_config { |
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mem_addr_t base; |
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const struct pinctrl_dev_config *pincfg; |
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uint8_t filter_clock_prescaler; |
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uint8_t max_filter_counter[CONFIG_NXP_S32_EIRQ_EXT_INTERRUPTS_MAX]; |
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}; |
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struct eirq_nxp_s32_cb { |
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eirq_nxp_s32_callback_t cb; |
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uint8_t pin; |
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void *data; |
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}; |
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struct eirq_nxp_s32_data { |
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struct eirq_nxp_s32_cb *cb; |
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}; |
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static inline void eirq_nxp_s32_interrupt_handler(const struct device *dev, uint32_t irq_idx) |
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{ |
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const struct eirq_nxp_s32_config *config = dev->config; |
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struct eirq_nxp_s32_data *data = dev->data; |
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uint32_t mask = GENMASK(CONFIG_NXP_S32_EIRQ_EXT_INTERRUPTS_GROUP - 1, 0); |
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uint32_t pending; |
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uint8_t irq; |
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pending = eirq_nxp_s32_get_pending(dev); |
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pending &= mask << (irq_idx * CONFIG_NXP_S32_EIRQ_EXT_INTERRUPTS_GROUP); |
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while (pending) { |
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mask = LSB_GET(pending); |
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irq = u64_count_trailing_zeros(mask); |
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/* Clear status flag */ |
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REG_WRITE(SIUL2_DISR0, REG_READ(SIUL2_DISR0) | mask); |
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if (data->cb[irq].cb != NULL) { |
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data->cb[irq].cb(data->cb[irq].pin, data->cb[irq].data); |
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} |
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pending ^= mask; |
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} |
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} |
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int eirq_nxp_s32_set_callback(const struct device *dev, uint8_t irq, uint8_t pin, |
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eirq_nxp_s32_callback_t cb, void *arg) |
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{ |
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struct eirq_nxp_s32_data *data = dev->data; |
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__ASSERT_NO_MSG(irq < CONFIG_NXP_S32_EIRQ_EXT_INTERRUPTS_MAX); |
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if ((data->cb[irq].cb == cb) && (data->cb[irq].data == arg)) { |
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return 0; |
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} |
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if (data->cb[irq].cb) { |
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return -EBUSY; |
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} |
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data->cb[irq].cb = cb; |
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data->cb[irq].pin = pin; |
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data->cb[irq].data = arg; |
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return 0; |
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} |
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void eirq_nxp_s32_unset_callback(const struct device *dev, uint8_t irq) |
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{ |
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struct eirq_nxp_s32_data *data = dev->data; |
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__ASSERT_NO_MSG(irq < CONFIG_NXP_S32_EIRQ_EXT_INTERRUPTS_MAX); |
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data->cb[irq].cb = NULL; |
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data->cb[irq].pin = 0; |
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data->cb[irq].data = NULL; |
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} |
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void eirq_nxp_s32_enable_interrupt(const struct device *dev, uint8_t irq, |
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enum eirq_nxp_s32_trigger trigger) |
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{ |
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const struct eirq_nxp_s32_config *config = dev->config; |
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uint32_t reg_val; |
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__ASSERT_NO_MSG(irq < CONFIG_NXP_S32_EIRQ_EXT_INTERRUPTS_MAX); |
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/* Configure trigger */ |
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reg_val = REG_READ(SIUL2_IREER0); |
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if ((trigger == EIRQ_NXP_S32_RISING_EDGE) || (trigger == EIRQ_NXP_S32_BOTH_EDGES)) { |
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reg_val |= BIT(irq); |
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} else { |
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reg_val &= ~BIT(irq); |
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} |
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REG_WRITE(SIUL2_IREER0, reg_val); |
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reg_val = REG_READ(SIUL2_IFEER0); |
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if ((trigger == EIRQ_NXP_S32_FALLING_EDGE) || (trigger == EIRQ_NXP_S32_BOTH_EDGES)) { |
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reg_val |= BIT(irq); |
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} else { |
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reg_val &= ~BIT(irq); |
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} |
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REG_WRITE(SIUL2_IFEER0, reg_val); |
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/* Clear status flag and unmask interrupt */ |
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REG_WRITE(SIUL2_DISR0, REG_READ(SIUL2_DISR0) | BIT(irq)); |
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REG_WRITE(SIUL2_DIRER0, REG_READ(SIUL2_DIRER0) | BIT(irq)); |
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} |
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void eirq_nxp_s32_disable_interrupt(const struct device *dev, uint8_t irq) |
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{ |
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const struct eirq_nxp_s32_config *config = dev->config; |
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__ASSERT_NO_MSG(irq < CONFIG_NXP_S32_EIRQ_EXT_INTERRUPTS_MAX); |
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/* Disable triggers */ |
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REG_WRITE(SIUL2_IREER0, REG_READ(SIUL2_IREER0) & ~BIT(irq)); |
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REG_WRITE(SIUL2_IFEER0, REG_READ(SIUL2_IFEER0) & ~BIT(irq)); |
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/* Clear status flag and mask interrupt */ |
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REG_WRITE(SIUL2_DISR0, REG_READ(SIUL2_DISR0) | BIT(irq)); |
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REG_WRITE(SIUL2_DIRER0, REG_READ(SIUL2_DIRER0) & ~BIT(irq)); |
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} |
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uint32_t eirq_nxp_s32_get_pending(const struct device *dev) |
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{ |
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const struct eirq_nxp_s32_config *config = dev->config; |
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return REG_READ(SIUL2_DISR0) & REG_READ(SIUL2_DIRER0); |
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} |
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static int eirq_nxp_s32_init(const struct device *dev) |
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{ |
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const struct eirq_nxp_s32_config *config = dev->config; |
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uint8_t irq; |
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int err; |
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err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); |
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if (err) { |
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return err; |
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} |
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/* Disable triggers, clear status flags and mask all interrupts */ |
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REG_WRITE(SIUL2_IREER0, 0U); |
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REG_WRITE(SIUL2_IFEER0, 0U); |
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REG_WRITE(SIUL2_DISR0, 0xffffffff); |
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REG_WRITE(SIUL2_DIRER0, 0U); |
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/* Select the request type as interrupt */ |
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REG_WRITE(SIUL2_DIRSR0, 0U); |
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/* Configure glitch filters */ |
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REG_WRITE(SIUL2_IFCPR, SIUL2_IFCPR_IFCP(config->filter_clock_prescaler)); |
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for (irq = 0; irq < CONFIG_NXP_S32_EIRQ_EXT_INTERRUPTS_MAX; irq++) { |
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if (config->max_filter_counter[irq] < GLITCH_FILTER_DISABLED) { |
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REG_WRITE(SIUL2_IFMCR(irq), |
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SIUL2_IFMCR_MAXCNT(config->max_filter_counter[irq])); |
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REG_WRITE(SIUL2_IFER0, REG_READ(SIUL2_IFER0) | BIT(irq)); |
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} else { |
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REG_WRITE(SIUL2_IFER0, REG_READ(SIUL2_IFER0) & ~BIT(irq)); |
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} |
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} |
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return 0; |
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} |
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#define EIRQ_NXP_S32_ISR_DEFINE(idx, n) \ |
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static void eirq_nxp_s32_isr##idx##_##n(const struct device *dev) \ |
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{ \ |
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eirq_nxp_s32_interrupt_handler(dev, idx); \ |
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} |
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#define _EIRQ_NXP_S32_IRQ_CONFIG(idx, n) \ |
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do { \ |
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, idx, irq), DT_INST_IRQ_BY_IDX(n, idx, priority), \ |
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eirq_nxp_s32_isr##idx##_##n, DEVICE_DT_INST_GET(n), \ |
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COND_CODE_1(CONFIG_GIC, (DT_INST_IRQ_BY_IDX(n, idx, flags)), (0))); \ |
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irq_enable(DT_INST_IRQ_BY_IDX(n, idx, irq)); \ |
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} while (false); |
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#define EIRQ_NXP_S32_IRQ_CONFIG(n) \ |
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LISTIFY(DT_NUM_IRQS(DT_DRV_INST(n)), _EIRQ_NXP_S32_IRQ_CONFIG, (), n) |
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#define EIRQ_NXP_S32_FILTER_CONFIG(idx, n) \ |
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COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(n, irq_##idx)), \ |
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(DT_PROP_OR(DT_INST_CHILD(n, irq_##idx), max_filter_counter, \ |
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GLITCH_FILTER_DISABLED)), \ |
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(GLITCH_FILTER_DISABLED)) |
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#define EIRQ_NXP_S32_INIT_DEVICE(n) \ |
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LISTIFY(DT_NUM_IRQS(DT_DRV_INST(n)), EIRQ_NXP_S32_ISR_DEFINE, (), n) \ |
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PINCTRL_DT_INST_DEFINE(n); \ |
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static const struct eirq_nxp_s32_config eirq_nxp_s32_conf_##n = { \ |
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.base = DT_INST_REG_ADDR(n), \ |
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.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ |
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.filter_clock_prescaler = DT_INST_PROP_OR(n, filter_prescaler, 0), \ |
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.max_filter_counter = {LISTIFY(CONFIG_NXP_S32_EIRQ_EXT_INTERRUPTS_MAX, \ |
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EIRQ_NXP_S32_FILTER_CONFIG, (,), n)}, \ |
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}; \ |
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static struct eirq_nxp_s32_cb eirq_nxp_s32_cb_##n[CONFIG_NXP_S32_EIRQ_EXT_INTERRUPTS_MAX]; \ |
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static struct eirq_nxp_s32_data eirq_nxp_s32_data_##n = { \ |
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.cb = eirq_nxp_s32_cb_##n, \ |
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}; \ |
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static int eirq_nxp_s32_init_##n(const struct device *dev) \ |
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{ \ |
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int err; \ |
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\ |
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err = eirq_nxp_s32_init(dev); \ |
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if (err) { \ |
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return err; \ |
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} \ |
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\ |
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EIRQ_NXP_S32_IRQ_CONFIG(n); \ |
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\ |
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return 0; \ |
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} \ |
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DEVICE_DT_INST_DEFINE(n, eirq_nxp_s32_init_##n, NULL, &eirq_nxp_s32_data_##n, \ |
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&eirq_nxp_s32_conf_##n, PRE_KERNEL_2, CONFIG_INTC_INIT_PRIORITY, \ |
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NULL); |
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DT_INST_FOREACH_STATUS_OKAY(EIRQ_NXP_S32_INIT_DEVICE)
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