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125 lines
2.9 KiB
125 lines
2.9 KiB
/* |
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* Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com> |
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* Copyright (c) 2025 Andes Technology Corporation |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_CLIC_H_ |
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#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_CLIC_H_ |
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/* CLIC relative CSR number */ |
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#define CSR_MTVT (0x307) |
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#define CSR_MNXTI (0x345) |
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#define CSR_MINTTHRESH (0x347) |
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#define CSR_MISELECT (0x350) |
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#define CSR_MIREG (0x351) |
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#define CSR_MIREG2 (0x352) |
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#ifndef __ASSEMBLER__ |
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#include <stddef.h> |
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#ifdef CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS |
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/* CLIC Memory mapped register offset */ |
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#define CLIC_CFG (0x0) |
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#define CLIC_CTRL(irq) (0x1000 + 4 * (irq)) |
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#define CLIC_INTIP(irq) (CLIC_CTRL(irq) + offsetof(union CLICCTRL, w.INTIP)) |
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#define CLIC_INTIE(irq) (CLIC_CTRL(irq) + offsetof(union CLICCTRL, w.INTIE)) |
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#define CLIC_INTATTR(irq) (CLIC_CTRL(irq) + offsetof(union CLICCTRL, w.INTATTR)) |
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#define CLIC_INTCTRL(irq) (CLIC_CTRL(irq) + offsetof(union CLICCTRL, w.INTCTRL)) |
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#else |
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/* Indirect CSR Access miselect offset */ |
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#define CLIC_CFG (0x14A0) |
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#define CLIC_CTRL(irq) (0x0) /* Dummy value for driver compatibility */ |
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#define CLIC_INTIP(irq) (0x1400 + (irq) / 32) |
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#define CLIC_INTIE(irq) (0x1400 + (irq) / 32) |
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#define CLIC_INTATTR(irq) (0x1000 + (irq) / 4) |
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#define CLIC_INTCTRL(irq) (0x1000 + (irq) / 4) |
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#endif /* !CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS */ |
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/* Nuclei ECLIC memory mapped register offset */ |
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#define CLIC_INFO (0x4) |
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#define CLIC_MTH (0x8) |
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/* CLIC register structure */ |
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union CLICCFG { |
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struct { |
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#ifdef CONFIG_NUCLEI_ECLIC |
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uint32_t _reserved0: 1; |
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#endif /* CONFIG_NUCLEI_ECLIC */ |
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/** number of interrupt level bits */ |
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uint32_t nlbits: 4; |
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/** number of clicintattr[i].MODE bits */ |
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uint32_t nmbits: 2; |
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uint32_t _reserved1: 25; |
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} w; |
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uint32_t qw; |
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}; |
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union CLICINTIP { |
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struct { |
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/** Interrupt Pending */ |
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uint8_t IP: 1; |
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uint8_t reserved0: 7; |
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} b; |
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uint8_t w; |
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}; |
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union CLICINTIE { |
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struct { |
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/** Interrupt Enabled */ |
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uint8_t IE: 1; |
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uint8_t reserved0: 7; |
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} b; |
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uint8_t w; |
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}; |
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union CLICINTATTR { |
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struct { |
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/** 0: non-vectored 1:vectored */ |
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uint8_t shv: 1; |
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/** 0: level 1: rising edge 2: falling edge */ |
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uint8_t trg: 2; |
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uint8_t reserved0: 3; |
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uint8_t mode: 2; |
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} b; |
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uint8_t w; |
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}; |
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union CLICCTRL { |
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struct { |
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volatile union CLICINTIP INTIP; |
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volatile union CLICINTIE INTIE; |
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volatile union CLICINTATTR INTATTR; |
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volatile uint8_t INTCTRL; |
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} w; |
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uint32_t qw; |
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}; |
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/* Nuclei ECLIC register structure */ |
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union CLICINFO { |
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struct { |
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/** number of max supported interrupts */ |
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uint32_t numint: 13; |
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/** architecture version */ |
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uint32_t version: 8; |
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/** supported bits in the clicintctl */ |
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uint32_t intctlbits: 4; |
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uint32_t _reserved0: 7; |
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} b; |
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uint32_t qw; |
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}; |
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union CLICMTH { |
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struct { |
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uint32_t reserved0: 24; |
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/** machine mode interrupt level threshold */ |
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uint32_t mth: 8; |
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} b; |
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uint32_t qw; |
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}; |
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#endif /*__ASSEMBLER__*/ |
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#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_CLIC_H_ */
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