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44 lines
1.2 KiB
44 lines
1.2 KiB
# Copyright (c) 2019 Intel Corporation |
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# SPDX-License-Identifier: Apache-2.0 |
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config DW_ICTL_ACE |
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bool "Designware Interrupt Controller for ACE" |
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default y |
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depends on DT_HAS_INTEL_ACE_INTC_ENABLED |
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depends on MULTI_LEVEL_INTERRUPTS |
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help |
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Designware Interrupt Controller used by ACE. |
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menuconfig DW_ICTL |
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bool "Designware Interrupt Controller" |
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default y |
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depends on DT_HAS_SNPS_DESIGNWARE_INTC_ENABLED |
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depends on MULTI_LEVEL_INTERRUPTS |
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help |
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Designware Interrupt Controller can be used as a 2nd level interrupt |
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controller which combines several sources of interrupt into one line |
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that is then routed to the 1st level interrupt controller. |
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if DW_ICTL |
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config DW_ICTL_NAME |
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string "Name for Designware Interrupt Controller" |
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default "DW_ICTL" |
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help |
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Give a name for the instance of Designware Interrupt Controller |
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config DW_ISR_TBL_OFFSET |
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int "Offset in the SW ISR Table" |
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default 0 |
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help |
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This indicates the offset in the SW_ISR_TABLE beginning from where |
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the ISRs for Designware Interrupt Controller are assigned. |
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config DW_ICTL_INIT_PRIORITY |
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int "Init priority for DW interrupt controller" |
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default 48 |
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help |
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DesignWare Interrupt Controller initialization priority. |
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endif # DW_ICTL
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