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280 lines
7.7 KiB
280 lines
7.7 KiB
/* |
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* Copyright (c) 2024 Michael Hope |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <zephyr/drivers/clock_control.h> |
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#include <zephyr/drivers/gpio.h> |
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#include <zephyr/drivers/gpio/gpio_utils.h> |
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#include <zephyr/drivers/interrupt_controller/wch_exti.h> |
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#include <zephyr/dt-bindings/gpio/gpio.h> |
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#include <zephyr/irq.h> |
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#include <hal_ch32fun.h> |
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#define DT_DRV_COMPAT wch_gpio |
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struct gpio_ch32v00x_config { |
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struct gpio_driver_config common; |
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GPIO_TypeDef *regs; |
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const struct device *clock_dev; |
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uint8_t clock_id; |
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}; |
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struct gpio_ch32v00x_data { |
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struct gpio_driver_data common; |
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sys_slist_t callbacks; |
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}; |
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static int gpio_ch32v00x_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) |
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{ |
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const struct gpio_ch32v00x_config *config = dev->config; |
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GPIO_TypeDef *regs = config->regs; |
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uint32_t cnf_mode; |
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uint32_t bshr = 0; |
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if ((flags & GPIO_OUTPUT) != 0) { |
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cnf_mode = 0x01; |
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) { |
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bshr = 1 << pin; |
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) { |
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bshr = 1 << (16 + pin); |
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} |
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} else if ((flags & GPIO_INPUT) != 0) { |
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if ((flags & GPIO_PULL_UP) != 0) { |
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cnf_mode = GPIO_CFGLR_IN_PUPD; |
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bshr = 1 << pin; |
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} else if ((flags & GPIO_PULL_DOWN) != 0) { |
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cnf_mode = GPIO_CFGLR_IN_PUPD; |
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bshr = 1 << (16 + pin); |
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} else { |
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cnf_mode = GPIO_CFGLR_IN_FLOAT; |
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} |
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} else { |
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cnf_mode = 0x00; |
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} |
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if (pin < 8) { |
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regs->CFGLR = (regs->CFGLR & ~(0x0F << (4 * pin))) | (cnf_mode << (4 * pin)); |
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} else { |
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regs->CFGHR = |
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(regs->CFGHR & ~(0x0F << ((pin - 8) * 4))) | (cnf_mode << ((pin - 8) * 4)); |
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} |
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regs->BSHR = bshr; |
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return 0; |
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} |
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static int gpio_ch32v00x_port_get_raw(const struct device *dev, uint32_t *value) |
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{ |
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const struct gpio_ch32v00x_config *config = dev->config; |
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*value = config->regs->INDR; |
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return 0; |
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} |
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static int gpio_ch32v00x_port_set_masked_raw(const struct device *dev, uint32_t mask, |
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uint32_t value) |
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{ |
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const struct gpio_ch32v00x_config *config = dev->config; |
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config->regs->BSHR = ((~value & mask) << 16) | (value & mask); |
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return 0; |
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} |
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static int gpio_ch32v00x_port_set_bits_raw(const struct device *dev, uint32_t pins) |
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{ |
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const struct gpio_ch32v00x_config *config = dev->config; |
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config->regs->BSHR = pins; |
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return 0; |
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} |
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static int gpio_ch32v00x_port_clear_bits_raw(const struct device *dev, uint32_t pins) |
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{ |
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const struct gpio_ch32v00x_config *config = dev->config; |
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config->regs->BCR = pins; |
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return 0; |
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} |
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static int gpio_ch32v00x_port_toggle_bits(const struct device *dev, uint32_t pins) |
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{ |
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const struct gpio_ch32v00x_config *config = dev->config; |
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uint32_t current = config->regs->OUTDR; |
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config->regs->BSHR = (~current & pins) | (current & pins) << 16; |
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return 0; |
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} |
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#if defined(CONFIG_GPIO_WCH_GPIO_INTERRUPTS) |
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static void gpio_ch32v00x_isr(uint8_t line, void *user) |
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{ |
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const struct device *dev = user; |
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struct gpio_ch32v00x_data *data = dev->data; |
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gpio_fire_callbacks(&data->callbacks, dev, BIT(line)); |
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} |
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static int gpio_ch32v00x_configure_exti(const struct device *dev, gpio_pin_t pin) |
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{ |
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const struct gpio_ch32v00x_config *config = dev->config; |
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AFIO_TypeDef *afio = (AFIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(pinctrl)); |
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uint8_t port_id; |
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uint8_t cr_id; |
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uint8_t bit0; |
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/* Convert the device into a port ID by checking the address */ |
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switch ((uintptr_t)config->regs) { |
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case DT_REG_ADDR(DT_NODELABEL(gpioa)): |
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port_id = 0; |
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break; |
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#if DT_NODE_EXISTS(DT_NODELABEL(gpiob)) |
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case DT_REG_ADDR(DT_NODELABEL(gpiob)): |
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port_id = 1; |
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break; |
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#endif |
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case DT_REG_ADDR(DT_NODELABEL(gpioc)): |
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port_id = 2; |
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break; |
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case DT_REG_ADDR(DT_NODELABEL(gpiod)): |
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port_id = 3; |
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break; |
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#if DT_NODE_EXISTS(DT_NODELABEL(gpioe)) |
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case DT_REG_ADDR(DT_NODELABEL(gpioe)): |
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port_id = 4; |
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break; |
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#endif |
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default: |
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return -EINVAL; |
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} |
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#if defined(AFIO_EXTICR_EXTI0) |
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/* CH32V003 style with one register with 2 bits per map. */ |
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BUILD_ASSERT(AFIO_EXTICR_EXTI0 == 0x03); |
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(void)cr_id; |
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bit0 = pin << 1; |
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afio->EXTICR = (afio->EXTICR & ~(AFIO_EXTICR_EXTI0 << bit0)) | (port_id << bit0); |
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#elif defined(AFIO_EXTICR1_EXTI0) |
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/* |
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* CH32V20x style with multiple registers with 4 pins per register and 4 bits per |
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* map. |
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*/ |
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BUILD_ASSERT(AFIO_EXTICR1_EXTI0 == 0x0F); |
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BUILD_ASSERT(ARRAY_SIZE(afio->EXTICR) == 4); |
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cr_id = pin / 4; |
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bit0 = (pin % 4) * 4; |
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afio->EXTICR[cr_id] = |
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(afio->EXTICR[cr_id] & ~(AFIO_EXTICR1_EXTI0 << bit0)) | (port_id << bit0); |
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#else |
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#error Unrecognised EXTICR format |
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#endif |
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return 0; |
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} |
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static int gpio_ch32v00x_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin, |
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enum gpio_int_mode mode, |
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enum gpio_int_trig trigger) |
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{ |
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int err; |
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switch (mode) { |
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case GPIO_INT_MODE_DISABLED: |
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wch_exti_disable(pin); |
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err = wch_exti_configure(pin, NULL, NULL); |
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break; |
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case GPIO_INT_MODE_EDGE: |
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err = wch_exti_configure(pin, gpio_ch32v00x_isr, (void *)dev); |
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if (err != 0) { |
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break; |
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} |
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err = gpio_ch32v00x_configure_exti(dev, pin); |
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if (err != 0) { |
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break; |
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} |
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switch (trigger) { |
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case GPIO_INT_TRIG_LOW: |
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wch_exti_set_trigger(pin, WCH_EXTI_TRIGGER_FALLING_EDGE); |
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break; |
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case GPIO_INT_TRIG_HIGH: |
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wch_exti_set_trigger(pin, WCH_EXTI_TRIGGER_RISING_EDGE); |
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break; |
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case GPIO_INT_TRIG_BOTH: |
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wch_exti_set_trigger(pin, WCH_EXTI_TRIGGER_FALLING_EDGE | |
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WCH_EXTI_TRIGGER_RISING_EDGE); |
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break; |
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default: |
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return -ENOTSUP; |
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} |
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wch_exti_enable(pin); |
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break; |
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default: |
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return -ENOTSUP; |
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} |
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return err; |
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} |
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static int gpio_ch32v00x_manage_callback(const struct device *dev, struct gpio_callback *callback, |
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bool set) |
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{ |
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struct gpio_ch32v00x_data *data = dev->data; |
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return gpio_manage_callback(&data->callbacks, callback, set); |
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} |
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#endif /* CONFIG_GPIO_WCH_GPIO_INTERRUPTS */ |
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static DEVICE_API(gpio, gpio_ch32v00x_driver_api) = { |
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.pin_configure = gpio_ch32v00x_configure, |
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.port_get_raw = gpio_ch32v00x_port_get_raw, |
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.port_set_masked_raw = gpio_ch32v00x_port_set_masked_raw, |
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.port_set_bits_raw = gpio_ch32v00x_port_set_bits_raw, |
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.port_clear_bits_raw = gpio_ch32v00x_port_clear_bits_raw, |
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.port_toggle_bits = gpio_ch32v00x_port_toggle_bits, |
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#if defined(CONFIG_GPIO_WCH_GPIO_INTERRUPTS) |
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.pin_interrupt_configure = gpio_ch32v00x_pin_interrupt_configure, |
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.manage_callback = gpio_ch32v00x_manage_callback, |
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#endif |
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}; |
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static int gpio_ch32v00x_init(const struct device *dev) |
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{ |
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const struct gpio_ch32v00x_config *config = dev->config; |
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clock_control_on(config->clock_dev, (clock_control_subsys_t *)(uintptr_t)config->clock_id); |
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return 0; |
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} |
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#define GPIO_CH32V00X_INIT(idx) \ |
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static const struct gpio_ch32v00x_config gpio_ch32v00x_##idx##_config = { \ |
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.common = \ |
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{ \ |
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx), \ |
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}, \ |
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.regs = (GPIO_TypeDef *)DT_INST_REG_ADDR(idx), \ |
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \ |
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.clock_id = DT_INST_CLOCKS_CELL(idx, id), \ |
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}; \ |
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\ |
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static struct gpio_ch32v00x_data gpio_ch32v00x_##idx##_data; \ |
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\ |
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DEVICE_DT_INST_DEFINE(idx, gpio_ch32v00x_init, NULL, &gpio_ch32v00x_##idx##_data, \ |
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&gpio_ch32v00x_##idx##_config, PRE_KERNEL_1, \ |
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CONFIG_GPIO_INIT_PRIORITY, &gpio_ch32v00x_driver_api); |
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DT_INST_FOREACH_STATUS_OKAY(GPIO_CH32V00X_INIT)
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