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268 lines
7.9 KiB
268 lines
7.9 KiB
/* |
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* Copyright (c) 2023-2024 Analog Devices, Inc. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <zephyr/drivers/clock_control.h> |
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#include <zephyr/drivers/gpio/gpio_utils.h> |
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#include <zephyr/kernel.h> |
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#include <zephyr/logging/log.h> |
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#include <zephyr/drivers/clock_control/adi_max32_clock_control.h> |
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#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h> |
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#include <gpio.h> |
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#define DT_DRV_COMPAT adi_max32_gpio |
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LOG_MODULE_REGISTER(gpio_max32, CONFIG_GPIO_LOG_LEVEL); |
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struct max32_gpio_config { |
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struct gpio_driver_config common; |
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mxc_gpio_regs_t *regs; |
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const struct device *clock; |
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void (*irq_func)(void); |
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struct max32_perclk perclk; |
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}; |
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struct max32_gpio_data { |
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struct gpio_driver_data common; |
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sys_slist_t cb_list; |
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}; |
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static int api_port_get_raw(const struct device *dev, uint32_t *value) |
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{ |
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const struct max32_gpio_config *cfg = dev->config; |
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*value = MXC_GPIO_InGet(cfg->regs, (unsigned int)-1); |
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return 0; |
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} |
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static int api_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, |
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gpio_port_value_t value) |
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{ |
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const struct max32_gpio_config *cfg = dev->config; |
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MXC_GPIO_OutPut(cfg->regs, mask, value); |
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return 0; |
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} |
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static int api_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins) |
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{ |
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const struct max32_gpio_config *cfg = dev->config; |
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MXC_GPIO_OutSet(cfg->regs, pins); |
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return 0; |
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} |
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static int api_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins) |
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{ |
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const struct max32_gpio_config *cfg = dev->config; |
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MXC_GPIO_OutClr(cfg->regs, pins); |
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return 0; |
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} |
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static int api_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins) |
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{ |
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const struct max32_gpio_config *cfg = dev->config; |
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MXC_GPIO_OutToggle(cfg->regs, pins); |
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return 0; |
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} |
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static int api_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) |
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{ |
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const struct max32_gpio_config *cfg = dev->config; |
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mxc_gpio_cfg_t gpio_cfg; |
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int ret; |
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/* MAX32xxx MCUs does not support SINGLE_ENDED, open drain, mode */ |
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if (flags & GPIO_SINGLE_ENDED) { |
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return -ENOTSUP; |
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} |
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gpio_cfg.port = cfg->regs; |
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gpio_cfg.mask = BIT(pin); |
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if (flags & GPIO_PULL_UP) { |
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gpio_cfg.pad = MXC_GPIO_PAD_PULL_UP; |
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} else if (flags & GPIO_PULL_DOWN) { |
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gpio_cfg.pad = MXC_GPIO_PAD_PULL_DOWN; |
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} else if (flags & MAX32_GPIO_WEAK_PULL_UP) { |
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gpio_cfg.pad = MXC_GPIO_PAD_WEAK_PULL_UP; |
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} else if (flags & MAX32_GPIO_WEAK_PULL_DOWN) { |
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gpio_cfg.pad = MXC_GPIO_PAD_WEAK_PULL_DOWN; |
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} else { |
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gpio_cfg.pad = MXC_GPIO_PAD_NONE; |
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} |
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if (flags & GPIO_OUTPUT) { |
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gpio_cfg.func = MXC_GPIO_FUNC_OUT; |
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} else if (flags & GPIO_INPUT) { |
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gpio_cfg.func = MXC_GPIO_FUNC_IN; |
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} else { |
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gpio_cfg.func = MXC_GPIO_FUNC_IN; |
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gpio_cfg.pad = MXC_GPIO_PAD_NONE; |
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} |
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if (flags & MAX32_GPIO_VSEL_VDDIOH) { |
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gpio_cfg.vssel = MXC_GPIO_VSSEL_VDDIOH; |
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} else { |
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gpio_cfg.vssel = MXC_GPIO_VSSEL_VDDIO; |
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} |
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switch (flags & MAX32_GPIO_DRV_STRENGTH_MASK) { |
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case MAX32_GPIO_DRV_STRENGTH_1: |
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gpio_cfg.drvstr = MXC_GPIO_DRVSTR_1; |
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break; |
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case MAX32_GPIO_DRV_STRENGTH_2: |
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gpio_cfg.drvstr = MXC_GPIO_DRVSTR_2; |
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break; |
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case MAX32_GPIO_DRV_STRENGTH_3: |
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gpio_cfg.drvstr = MXC_GPIO_DRVSTR_3; |
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break; |
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default: |
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gpio_cfg.drvstr = MXC_GPIO_DRVSTR_0; |
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break; |
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} |
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ret = MXC_GPIO_Config(&gpio_cfg); |
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if (ret != 0) { |
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return -ENOTSUP; |
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} |
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if (flags & GPIO_OUTPUT) { |
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if (flags & GPIO_OUTPUT_INIT_LOW) { |
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MXC_GPIO_OutClr(cfg->regs, BIT(pin)); |
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} else if (flags & GPIO_OUTPUT_INIT_HIGH) { |
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MXC_GPIO_OutSet(cfg->regs, BIT(pin)); |
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} |
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} |
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return 0; |
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} |
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static int api_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin, |
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enum gpio_int_mode mode, enum gpio_int_trig trig) |
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{ |
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const struct max32_gpio_config *cfg = dev->config; |
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mxc_gpio_cfg_t gpio_cfg; |
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gpio_cfg.port = cfg->regs; |
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gpio_cfg.mask = BIT(pin); |
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/* rest of the parameters not necessary */ |
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if (mode == GPIO_INT_MODE_DISABLED) { |
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MXC_GPIO_DisableInt(cfg->regs, gpio_cfg.mask); |
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/* clear interrupt flags */ |
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MXC_GPIO_ClearFlags(cfg->regs, (MXC_GPIO_GetFlags(cfg->regs) & gpio_cfg.mask)); |
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return 0; |
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} |
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switch (mode) { |
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case GPIO_INT_MODE_LEVEL: |
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if (trig == GPIO_INT_TRIG_LOW) { |
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MXC_GPIO_IntConfig(&gpio_cfg, MXC_GPIO_INT_LOW); |
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} else if (trig == GPIO_INT_TRIG_HIGH) { |
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MXC_GPIO_IntConfig(&gpio_cfg, MXC_GPIO_INT_HIGH); |
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} else if (trig == GPIO_INT_TRIG_BOTH) { |
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MXC_GPIO_IntConfig(&gpio_cfg, MXC_GPIO_INT_BOTH); |
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} else { |
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return -EINVAL; |
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} |
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break; |
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case GPIO_INT_MODE_EDGE: |
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if (trig == GPIO_INT_TRIG_LOW) { |
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MXC_GPIO_IntConfig(&gpio_cfg, MXC_GPIO_INT_FALLING); |
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} else if (trig == GPIO_INT_TRIG_HIGH) { |
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MXC_GPIO_IntConfig(&gpio_cfg, MXC_GPIO_INT_RISING); |
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} else if (trig == GPIO_INT_TRIG_BOTH) { |
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MXC_GPIO_IntConfig(&gpio_cfg, MXC_GPIO_INT_BOTH); |
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} else { |
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return -EINVAL; |
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} |
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break; |
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default: |
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return -EINVAL; |
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} |
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cfg->irq_func(); |
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MXC_GPIO_EnableInt(cfg->regs, gpio_cfg.mask); |
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return 0; |
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} |
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static int api_manage_callback(const struct device *dev, struct gpio_callback *callback, bool set) |
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{ |
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struct max32_gpio_data *data = dev->data; |
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return gpio_manage_callback(&(data->cb_list), callback, set); |
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} |
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static DEVICE_API(gpio, gpio_max32_driver) = { |
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.pin_configure = api_pin_configure, |
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.port_get_raw = api_port_get_raw, |
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.port_set_masked_raw = api_port_set_masked_raw, |
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.port_set_bits_raw = api_port_set_bits_raw, |
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.port_clear_bits_raw = api_port_clear_bits_raw, |
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.port_toggle_bits = api_port_toggle_bits, |
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.pin_interrupt_configure = api_pin_interrupt_configure, |
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.manage_callback = api_manage_callback, |
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}; |
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static void gpio_max32_isr(const void *param) |
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{ |
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const struct device *dev = param; |
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const struct max32_gpio_config *cfg = dev->config; |
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struct max32_gpio_data *data = dev->data; |
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unsigned int flags = MXC_GPIO_GetFlags(cfg->regs); |
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/* clear interrupt flags */ |
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MXC_GPIO_ClearFlags(cfg->regs, flags); |
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gpio_fire_callbacks(&(data->cb_list), dev, flags); |
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} |
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static int gpio_max32_init(const struct device *dev) |
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{ |
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int ret = 0; |
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const struct max32_gpio_config *cfg = dev->config; |
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if (cfg->clock != NULL) { |
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/* enable clock */ |
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ret = clock_control_on(cfg->clock, (clock_control_subsys_t)&cfg->perclk); |
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if (ret != 0) { |
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LOG_ERR("cannot enable GPIO clock"); |
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return ret; |
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} |
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} |
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return ret; |
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} |
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#define MAX32_GPIO_INIT(_num) \ |
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static void gpio_max32_irq_init_##_num(void) \ |
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{ \ |
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IRQ_CONNECT(DT_INST_IRQN(_num), DT_INST_IRQ(_num, priority), gpio_max32_isr, \ |
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DEVICE_DT_INST_GET(_num), 0); \ |
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irq_enable(DT_INST_IRQN(_num)); \ |
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} \ |
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static struct max32_gpio_data max32_gpio_data_##_num; \ |
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static const struct max32_gpio_config max32_gpio_config_##_num = { \ |
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.common = \ |
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{ \ |
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(_num), \ |
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}, \ |
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.regs = (mxc_gpio_regs_t *)DT_INST_REG_ADDR(_num), \ |
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.irq_func = &gpio_max32_irq_init_##_num, \ |
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.clock = DEVICE_DT_GET_OR_NULL(DT_INST_CLOCKS_CTLR(_num)), \ |
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.perclk.bus = DT_INST_PHA_BY_IDX_OR(_num, clocks, 0, offset, 0), \ |
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.perclk.bit = DT_INST_PHA_BY_IDX_OR(_num, clocks, 1, bit, 0), \ |
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}; \ |
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DEVICE_DT_INST_DEFINE(_num, gpio_max32_init, NULL, &max32_gpio_data_##_num, \ |
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&max32_gpio_config_##_num, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \ |
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(void *)&gpio_max32_driver); |
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DT_INST_FOREACH_STATUS_OKAY(MAX32_GPIO_INIT)
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