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734 lines
22 KiB
734 lines
22 KiB
/* |
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* Copyright (c) 2021 Volvo Construction Equipment |
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* Copyright 2023 NXP |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT nxp_imx_flexspi_hyperflash |
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#include <zephyr/kernel.h> |
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#include <errno.h> |
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#include <zephyr/drivers/flash.h> |
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#include <zephyr/logging/log.h> |
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/* |
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* NOTE: If CONFIG_FLASH_MCUX_FLEXSPI_XIP is selected, Any external functions |
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* called while interacting with the flexspi MUST be relocated to SRAM or ITCM |
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* at runtime, so that the chip does not access the flexspi to read program |
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* instructions while it is being written to |
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* |
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* Additionally, no data used by this driver should be stored in flash. |
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*/ |
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#if defined(CONFIG_FLASH_MCUX_FLEXSPI_XIP) && (CONFIG_FLASH_LOG_LEVEL > 0) |
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#warning "Enabling flash driver logging and XIP mode simultaneously can cause \ |
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read-while-write hazards. This configuration is not recommended." |
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#endif |
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LOG_MODULE_REGISTER(flexspi_hyperflash, CONFIG_FLASH_LOG_LEVEL); |
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#ifdef CONFIG_HAS_MCUX_CACHE |
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#include <fsl_cache.h> |
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#endif |
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#include <zephyr/sys/util.h> |
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#include "memc_mcux_flexspi.h" |
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#define SPI_HYPERFLASH_SECTOR_SIZE (0x40000U) |
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#define SPI_HYPERFLASH_PAGE_SIZE (512U) |
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#define HYPERFLASH_ERASE_VALUE (0xFF) |
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/* Hyper flash support SDR and DDR, from the FlexSPI controller point of view, |
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* if DDR enabled, commands in LUT need to be DDR command and root clock is |
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* double of Serial clock (clock output to flash). |
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* if DDR mode enabled, set it to 2 |
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* if SDR mode enabled, set it to 1 |
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*/ |
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#define MCUX_FLEXSPI_HYPERFLASH_DDR_SDR_MODE 2 |
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/* Some hyper flashs require a lower frequency when doing writing operation. */ |
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#define FREQ_FOR_HYPERFLASH_WRITE (MHZ(42) * MCUX_FLEXSPI_HYPERFLASH_DDR_SDR_MODE) |
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#ifdef CONFIG_FLASH_MCUX_FLEXSPI_HYPERFLASH_WRITE_BUFFER |
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static uint8_t hyperflash_write_buf[SPI_HYPERFLASH_PAGE_SIZE]; |
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#endif |
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enum { |
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/* Instructions matching with XIP layout */ |
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READ_DATA = 0, |
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WRITE_DATA = 1, |
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READ_STATUS = 2, |
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WRITE_ENABLE = 4, |
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ERASE_SECTOR = 6, |
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PAGE_PROGRAM = 10, |
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ERASE_CHIP = 12, |
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}; |
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#define CUSTOM_LUT_LENGTH 64 |
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static const uint32_t flash_flexspi_hyperflash_lut[CUSTOM_LUT_LENGTH] = { |
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/* Read Data */ |
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[4 * READ_DATA] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, |
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kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), |
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[4 * READ_DATA + 1] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, |
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kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0xC), |
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[4 * READ_DATA + 2] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, |
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0), |
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/* Write Data */ |
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[4 * WRITE_DATA] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, |
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kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), |
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[4 * WRITE_DATA + 1] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, |
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kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x02), |
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/* Read Status */ |
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[4 * READ_STATUS] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), |
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[4 * READ_STATUS + 1] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), |
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[4 * READ_STATUS + 2] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), |
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[4 * READ_STATUS + 3] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x70), |
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[4 * READ_STATUS + 4] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, |
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kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), |
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[4 * READ_STATUS + 5] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, |
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kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x0B), |
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[4 * READ_STATUS + 6] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, |
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0), |
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/* Write Enable */ |
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[4 * WRITE_ENABLE] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), |
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[4 * WRITE_ENABLE + 1] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), |
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[4 * WRITE_ENABLE + 2] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), |
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[4 * WRITE_ENABLE + 3] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), |
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[4 * WRITE_ENABLE + 4] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), |
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[4 * WRITE_ENABLE + 5] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), |
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[4 * WRITE_ENABLE + 6] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02), |
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[4 * WRITE_ENABLE + 7] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), |
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/* Erase Sector */ |
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[4 * ERASE_SECTOR] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), |
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[4 * ERASE_SECTOR + 1] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), |
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[4 * ERASE_SECTOR + 2] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), |
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[4 * ERASE_SECTOR + 3] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80), |
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[4 * ERASE_SECTOR + 4] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), |
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[4 * ERASE_SECTOR + 5] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), |
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[4 * ERASE_SECTOR + 6] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), |
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[4 * ERASE_SECTOR + 7] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), |
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[4 * ERASE_SECTOR + 8] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), |
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[4 * ERASE_SECTOR + 9] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), |
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[4 * ERASE_SECTOR + 10] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02), |
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[4 * ERASE_SECTOR + 11] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), |
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[4 * ERASE_SECTOR + 12] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), |
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[4 * ERASE_SECTOR + 13] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), |
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[4 * ERASE_SECTOR + 14] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x30, |
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00), |
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/* program page with word program command sequence */ |
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[4 * PAGE_PROGRAM] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), |
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[4 * PAGE_PROGRAM + 1] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), |
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[4 * PAGE_PROGRAM + 2] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), |
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[4 * PAGE_PROGRAM + 3] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0), |
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[4 * PAGE_PROGRAM + 4] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, |
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kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), |
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[4 * PAGE_PROGRAM + 5] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, |
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kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x80), |
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/* Erase chip */ |
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[4 * ERASE_CHIP] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), |
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[4 * ERASE_CHIP + 1] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), |
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[4 * ERASE_CHIP + 2] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), |
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[4 * ERASE_CHIP + 3] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80), |
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/* 1 */ |
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[4 * ERASE_CHIP + 4] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), |
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[4 * ERASE_CHIP + 5] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), |
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[4 * ERASE_CHIP + 6] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), |
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[4 * ERASE_CHIP + 7] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), |
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/* 2 */ |
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[4 * ERASE_CHIP + 8] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), |
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[4 * ERASE_CHIP + 9] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), |
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[4 * ERASE_CHIP + 10] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02), |
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[4 * ERASE_CHIP + 11] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), |
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/* 3 */ |
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[4 * ERASE_CHIP + 12] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), |
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[4 * ERASE_CHIP + 13] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), |
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[4 * ERASE_CHIP + 14] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), |
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[4 * ERASE_CHIP + 15] = |
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, |
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x10), |
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}; |
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struct flash_flexspi_hyperflash_config { |
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const struct device *controller; |
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}; |
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/* Device variables used in critical sections should be in this structure */ |
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struct flash_flexspi_hyperflash_data { |
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struct device controller; |
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flexspi_device_config_t config; |
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flexspi_port_t port; |
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struct flash_pages_layout layout; |
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struct flash_parameters flash_parameters; |
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}; |
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/* Make sure all parameters accessed by this function are in RAM when XIP is enabled. */ |
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static int flash_flexspi_hyperflash_wait_bus_busy(const struct flash_flexspi_hyperflash_data *data) |
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{ |
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flexspi_transfer_t transfer; |
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int ret; |
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bool is_busy; |
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uint32_t read_value; |
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transfer.deviceAddress = 0; |
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transfer.port = data->port; |
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transfer.cmdType = kFLEXSPI_Read; |
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transfer.SeqNumber = 2; |
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transfer.seqIndex = READ_STATUS; |
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transfer.data = &read_value; |
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transfer.dataSize = 2; |
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do { |
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ret = memc_flexspi_transfer(&data->controller, &transfer); |
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if (ret != 0) { |
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return ret; |
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} |
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is_busy = !(read_value & 0x8000); |
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|
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if (read_value & 0x3200) { |
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ret = -EINVAL; |
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break; |
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} |
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} while (is_busy); |
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return ret; |
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} |
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|
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/* Make sure all parameters accessed by this function are in RAM when XIP is enabled. */ |
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static int flash_flexspi_hyperflash_write_enable(const struct flash_flexspi_hyperflash_data *data, |
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uint32_t address) |
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{ |
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flexspi_transfer_t transfer; |
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int ret; |
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|
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transfer.deviceAddress = address; |
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transfer.port = data->port; |
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transfer.cmdType = kFLEXSPI_Command; |
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transfer.SeqNumber = 2; |
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transfer.seqIndex = WRITE_ENABLE; |
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|
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ret = memc_flexspi_transfer(&data->controller, &transfer); |
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|
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return ret; |
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} |
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|
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static int flash_flexspi_hyperflash_check_vendor_id(const struct device *dev) |
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{ |
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struct flash_flexspi_hyperflash_data *data = dev->data; |
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uint8_t writebuf[4] = {0x00, 0x98}; |
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uint32_t buffer[2]; |
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int ret; |
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flexspi_transfer_t transfer; |
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|
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transfer.deviceAddress = (0x555 * 2); |
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transfer.port = data->port; |
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transfer.cmdType = kFLEXSPI_Write; |
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transfer.SeqNumber = 1; |
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transfer.seqIndex = WRITE_DATA; |
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transfer.data = (uint32_t *)writebuf; |
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transfer.dataSize = 2; |
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|
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LOG_DBG("Reading id"); |
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|
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ret = memc_flexspi_transfer(&data->controller, &transfer); |
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if (ret != 0) { |
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LOG_ERR("failed to CFI"); |
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return ret; |
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} |
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|
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transfer.deviceAddress = (0x10 * 2); |
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transfer.port = data->port; |
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transfer.cmdType = kFLEXSPI_Read; |
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transfer.SeqNumber = 1; |
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transfer.seqIndex = READ_DATA; |
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transfer.data = buffer; |
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transfer.dataSize = 8; |
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|
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ret = memc_flexspi_transfer(&data->controller, &transfer); |
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if (ret != 0) { |
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LOG_ERR("failed to read id"); |
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return ret; |
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} |
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buffer[1] &= 0xFFFF; |
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/* Check that the data read out is unicode "QRY" in big-endian order */ |
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if ((buffer[0] != 0x52005100) || (buffer[1] != 0x5900)) { |
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LOG_ERR("data read out is wrong!"); |
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return -EINVAL; |
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} |
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|
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writebuf[1] = 0xF0; |
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transfer.deviceAddress = 0; |
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transfer.port = data->port; |
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transfer.cmdType = kFLEXSPI_Write; |
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transfer.SeqNumber = 1; |
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transfer.seqIndex = WRITE_DATA; |
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transfer.data = (uint32_t *)writebuf; |
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transfer.dataSize = 2; |
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|
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ret = memc_flexspi_transfer(&data->controller, &transfer); |
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if (ret != 0) { |
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LOG_ERR("failed to exit"); |
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return ret; |
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} |
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|
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memc_flexspi_reset(&data->controller); |
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|
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return ret; |
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} |
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|
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/* Make sure all parameters accessed by this function are in RAM when XIP is enabled. */ |
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static int flash_flexspi_hyperflash_page_program(const struct flash_flexspi_hyperflash_data *data, |
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off_t offset, const void *buffer, size_t len) |
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{ |
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flexspi_transfer_t transfer = { |
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.deviceAddress = offset, |
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.port = data->port, |
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.cmdType = kFLEXSPI_Write, |
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.SeqNumber = 2, |
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.seqIndex = PAGE_PROGRAM, |
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.data = (uint32_t *)buffer, |
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.dataSize = len, |
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}; |
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|
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LOG_DBG("Page programming %d bytes to 0x%08lx", len, offset); |
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|
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return memc_flexspi_transfer(&data->controller, &transfer); |
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} |
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|
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static int flash_flexspi_hyperflash_read(const struct device *dev, off_t offset, |
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void *buffer, size_t len) |
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{ |
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struct flash_flexspi_hyperflash_data *data = dev->data; |
|
|
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if (len == 0) { |
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return 0; |
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} |
|
|
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if (!buffer) { |
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return -EINVAL; |
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} |
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|
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uint8_t *src = memc_flexspi_get_ahb_address(&data->controller, |
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data->port, |
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offset); |
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if (!src) { |
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return -EINVAL; |
|
} |
|
|
|
memcpy(buffer, src, len); |
|
|
|
return 0; |
|
} |
|
|
|
static int flash_flexspi_hyperflash_write(const struct device *dev, off_t offset, |
|
const void *buffer, size_t len) |
|
{ |
|
struct flash_flexspi_hyperflash_data *data = dev->data; |
|
size_t size = len; |
|
uint8_t *src = (uint8_t *)buffer; |
|
unsigned int key = 0; |
|
int i, j; |
|
int ret = -1; |
|
|
|
uint8_t *dst = memc_flexspi_get_ahb_address(&data->controller, |
|
data->port, |
|
offset); |
|
if (!dst) { |
|
return -EINVAL; |
|
} |
|
|
|
if (memc_flexspi_is_running_xip(&data->controller)) { |
|
/* |
|
* ==== ENTER CRITICAL SECTION ==== |
|
* No flash access should be performed in critical section. All |
|
* code and data accessed must reside in ram. |
|
*/ |
|
key = irq_lock(); |
|
memc_flexspi_wait_bus_idle(&data->controller); |
|
} |
|
|
|
/* Update clock to a freq which usually lower than normal working freq. */ |
|
if (memc_flexspi_update_clock(&data->controller, &data->config, |
|
data->port, FREQ_FOR_HYPERFLASH_WRITE)) { |
|
ret = -ENOTSUP; |
|
goto __exit; |
|
} |
|
|
|
while (len) { |
|
/* Writing between two page sizes crashes the platform so we |
|
* have to write the part that fits in the first page and then |
|
* update the offset. |
|
*/ |
|
i = MIN(SPI_HYPERFLASH_PAGE_SIZE - (offset % |
|
SPI_HYPERFLASH_PAGE_SIZE), len); |
|
#ifdef CONFIG_FLASH_MCUX_FLEXSPI_HYPERFLASH_WRITE_BUFFER |
|
for (j = 0; j < i; j++) { |
|
hyperflash_write_buf[j] = src[j]; |
|
} |
|
#endif |
|
ret = flash_flexspi_hyperflash_write_enable(data, offset); |
|
if (ret != 0) { |
|
LOG_ERR("failed to enable write"); |
|
break; |
|
} |
|
#ifdef CONFIG_FLASH_MCUX_FLEXSPI_HYPERFLASH_WRITE_BUFFER |
|
ret = flash_flexspi_hyperflash_page_program(data, offset, |
|
hyperflash_write_buf, i); |
|
#else |
|
ret = flash_flexspi_hyperflash_page_program(data, offset, src, i); |
|
#endif |
|
if (ret != 0) { |
|
LOG_ERR("failed to write"); |
|
break; |
|
} |
|
|
|
ret = flash_flexspi_hyperflash_wait_bus_busy(data); |
|
if (ret != 0) { |
|
LOG_ERR("failed to wait bus busy"); |
|
break; |
|
} |
|
|
|
/* Do software reset. */ |
|
memc_flexspi_reset(&data->controller); |
|
src += i; |
|
offset += i; |
|
len -= i; |
|
} |
|
|
|
/* Clock FlexSPI at max freq flash support. */ |
|
if (memc_flexspi_update_clock(&data->controller, &data->config, |
|
data->port, data->config.flexspiRootClk)) { |
|
ret = -ENOTSUP; |
|
goto __exit; |
|
} |
|
|
|
#ifdef CONFIG_HAS_MCUX_CACHE |
|
DCACHE_InvalidateByRange((uint32_t) dst, size); |
|
#endif |
|
|
|
__exit: |
|
if (memc_flexspi_is_running_xip(&data->controller)) { |
|
/* ==== EXIT CRITICAL SECTION ==== */ |
|
irq_unlock(key); |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
static int flash_flexspi_hyperflash_erase(const struct device *dev, off_t offset, size_t size) |
|
{ |
|
struct flash_flexspi_hyperflash_data *data = dev->data; |
|
flexspi_transfer_t transfer; |
|
int ret = -1; |
|
int i; |
|
unsigned int key = 0; |
|
int num_sectors = size / SPI_HYPERFLASH_SECTOR_SIZE; |
|
uint8_t *dst = memc_flexspi_get_ahb_address(&data->controller, |
|
data->port, |
|
offset); |
|
|
|
if (!dst) { |
|
return -EINVAL; |
|
} |
|
|
|
if (offset % SPI_HYPERFLASH_SECTOR_SIZE) { |
|
LOG_ERR("Invalid offset"); |
|
return -EINVAL; |
|
} |
|
|
|
if (size % SPI_HYPERFLASH_SECTOR_SIZE) { |
|
LOG_ERR("Invalid offset"); |
|
return -EINVAL; |
|
} |
|
|
|
if (memc_flexspi_is_running_xip(&data->controller)) { |
|
/* |
|
* ==== ENTER CRITICAL SECTION ==== |
|
* No flash access should be performed in critical section. All |
|
* code and data accessed must reside in ram. |
|
*/ |
|
key = irq_lock(); |
|
memc_flexspi_wait_bus_idle(&data->controller); |
|
} |
|
|
|
for (i = 0; i < num_sectors; i++) { |
|
ret = flash_flexspi_hyperflash_write_enable(data, offset); |
|
if (ret != 0) { |
|
LOG_ERR("failed to write_enable"); |
|
break; |
|
} |
|
|
|
LOG_DBG("Erasing sector at 0x%08lx", offset); |
|
|
|
transfer.deviceAddress = offset; |
|
transfer.port = data->port; |
|
transfer.cmdType = kFLEXSPI_Command; |
|
transfer.SeqNumber = 4; |
|
transfer.seqIndex = ERASE_SECTOR; |
|
|
|
ret = memc_flexspi_transfer(&data->controller, &transfer); |
|
if (ret != 0) { |
|
LOG_ERR("failed to erase"); |
|
break; |
|
} |
|
|
|
/* wait bus busy */ |
|
ret = flash_flexspi_hyperflash_wait_bus_busy(data); |
|
if (ret != 0) { |
|
LOG_ERR("failed to wait bus busy"); |
|
break; |
|
} |
|
|
|
/* Do software reset. */ |
|
memc_flexspi_reset(&data->controller); |
|
|
|
offset += SPI_HYPERFLASH_SECTOR_SIZE; |
|
} |
|
|
|
#ifdef CONFIG_HAS_MCUX_CACHE |
|
DCACHE_InvalidateByRange((uint32_t) dst, size); |
|
#endif |
|
|
|
if (memc_flexspi_is_running_xip(&data->controller)) { |
|
/* ==== EXIT CRITICAL SECTION ==== */ |
|
irq_unlock(key); |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
static const struct flash_parameters *flash_flexspi_hyperflash_get_parameters( |
|
const struct device *dev) |
|
{ |
|
struct flash_flexspi_hyperflash_data *data = dev->data; |
|
|
|
return &data->flash_parameters; |
|
} |
|
|
|
|
|
static void flash_flexspi_hyperflash_pages_layout(const struct device *dev, |
|
const struct flash_pages_layout **layout, |
|
size_t *layout_size) |
|
{ |
|
struct flash_flexspi_hyperflash_data *data = dev->data; |
|
|
|
*layout = &data->layout; |
|
*layout_size = 1; |
|
} |
|
|
|
static int flash_flexspi_hyperflash_init(const struct device *dev) |
|
{ |
|
const struct flash_flexspi_hyperflash_config *config = dev->config; |
|
struct flash_flexspi_hyperflash_data *data = dev->data; |
|
|
|
/* Since the controller variable may be used in critical sections, |
|
* copy the device pointer into a variable stored in RAM |
|
*/ |
|
memcpy(&data->controller, config->controller, sizeof(struct device)); |
|
|
|
if (!device_is_ready(&data->controller)) { |
|
LOG_ERR("Controller device not ready"); |
|
return -ENODEV; |
|
} |
|
|
|
memc_flexspi_wait_bus_idle(&data->controller); |
|
|
|
if (memc_flexspi_set_device_config(&data->controller, &data->config, |
|
(const uint32_t *)flash_flexspi_hyperflash_lut, |
|
sizeof(flash_flexspi_hyperflash_lut) / MEMC_FLEXSPI_CMD_SIZE, |
|
data->port)) { |
|
LOG_ERR("Could not set device configuration"); |
|
return -EINVAL; |
|
} |
|
|
|
memc_flexspi_reset(&data->controller); |
|
|
|
if (flash_flexspi_hyperflash_check_vendor_id(dev)) { |
|
LOG_ERR("Could not read vendor id"); |
|
return -EIO; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static DEVICE_API(flash, flash_flexspi_hyperflash_api) = { |
|
.read = flash_flexspi_hyperflash_read, |
|
.write = flash_flexspi_hyperflash_write, |
|
.erase = flash_flexspi_hyperflash_erase, |
|
.get_parameters = flash_flexspi_hyperflash_get_parameters, |
|
#if defined(CONFIG_FLASH_PAGE_LAYOUT) |
|
.page_layout = flash_flexspi_hyperflash_pages_layout, |
|
#endif |
|
}; |
|
|
|
#define CONCAT3(x, y, z) x ## y ## z |
|
|
|
#define CS_INTERVAL_UNIT(unit) \ |
|
CONCAT3(kFLEXSPI_CsIntervalUnit, unit, SckCycle) |
|
|
|
#define AHB_WRITE_WAIT_UNIT(unit) \ |
|
CONCAT3(kFLEXSPI_AhbWriteWaitUnit, unit, AhbCycle) |
|
|
|
#define FLASH_FLEXSPI_DEVICE_CONFIG(n) \ |
|
{ \ |
|
.flexspiRootClk = DT_INST_PROP(n, spi_max_frequency) * \ |
|
MCUX_FLEXSPI_HYPERFLASH_DDR_SDR_MODE, \ |
|
.flashSize = DT_INST_PROP(n, size) / 8 / KB(1), \ |
|
.CSIntervalUnit = \ |
|
CS_INTERVAL_UNIT( \ |
|
DT_INST_PROP(n, cs_interval_unit)), \ |
|
.CSInterval = DT_INST_PROP(n, cs_interval), \ |
|
.CSHoldTime = DT_INST_PROP(n, cs_hold_time), \ |
|
.CSSetupTime = DT_INST_PROP(n, cs_setup_time), \ |
|
.dataValidTime = DT_INST_PROP(n, data_valid_time), \ |
|
.columnspace = DT_INST_PROP(n, column_space), \ |
|
.enableWordAddress = DT_INST_PROP(n, word_addressable), \ |
|
.AWRSeqIndex = WRITE_DATA, \ |
|
.AWRSeqNumber = 1, \ |
|
.ARDSeqIndex = READ_DATA, \ |
|
.ARDSeqNumber = 1, \ |
|
.AHBWriteWaitUnit = \ |
|
AHB_WRITE_WAIT_UNIT( \ |
|
DT_INST_PROP(n, ahb_write_wait_unit)), \ |
|
.AHBWriteWaitInterval = \ |
|
DT_INST_PROP(n, ahb_write_wait_interval), \ |
|
} \ |
|
|
|
#define FLASH_FLEXSPI_HYPERFLASH(n) \ |
|
static struct flash_flexspi_hyperflash_config \ |
|
flash_flexspi_hyperflash_config_##n = { \ |
|
.controller = DEVICE_DT_GET(DT_INST_BUS(n)), \ |
|
}; \ |
|
static struct flash_flexspi_hyperflash_data \ |
|
flash_flexspi_hyperflash_data_##n = { \ |
|
.config = FLASH_FLEXSPI_DEVICE_CONFIG(n), \ |
|
.port = DT_INST_REG_ADDR(n), \ |
|
.layout = { \ |
|
.pages_count = DT_INST_PROP(n, size) / 8 \ |
|
/ SPI_HYPERFLASH_SECTOR_SIZE, \ |
|
.pages_size = SPI_HYPERFLASH_SECTOR_SIZE, \ |
|
}, \ |
|
.flash_parameters = { \ |
|
.write_block_size = DT_INST_PROP(n, write_block_size), \ |
|
.erase_value = HYPERFLASH_ERASE_VALUE, \ |
|
}, \ |
|
}; \ |
|
\ |
|
DEVICE_DT_INST_DEFINE(n, \ |
|
flash_flexspi_hyperflash_init, \ |
|
NULL, \ |
|
&flash_flexspi_hyperflash_data_##n, \ |
|
&flash_flexspi_hyperflash_config_##n, \ |
|
POST_KERNEL, \ |
|
CONFIG_FLASH_INIT_PRIORITY, \ |
|
&flash_flexspi_hyperflash_api); |
|
|
|
DT_INST_FOREACH_STATUS_OKAY(FLASH_FLEXSPI_HYPERFLASH)
|
|
|