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270 lines
8.7 KiB
270 lines
8.7 KiB
/* |
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* Copyright (c) 2023, Intel Corporation. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT cdns_nand |
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#include "socfpga_system_manager.h" |
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#include <zephyr/device.h> |
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#include <zephyr/drivers/flash.h> |
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#include <zephyr/kernel.h> |
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/* Check if reset property is defined */ |
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#define CDNS_NAND_RESET_SUPPORT DT_ANY_INST_HAS_PROP_STATUS_OKAY(resets) |
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#if CDNS_NAND_RESET_SUPPORT |
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#include <zephyr/drivers/reset.h> |
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#endif |
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#include "flash_cadence_nand_ll.h" |
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#define DEV_CFG(_dev) ((const struct flash_cadence_nand_config *)(_dev)->config) |
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#define DEV_DATA(_dev) ((struct flash_cadence_nand_data *const)(_dev)->data) |
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#define FLASH_WRITE_SIZE DT_PROP(DT_INST(0, DT_DRV_COMPAT), block_size) |
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#ifdef CONFIG_BOARD_INTEL_SOCFPGA_AGILEX5_SOCDK |
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#define DFI_CFG_OFFSET 0xFC |
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/* To check the DFI register setting for NAND in the System Manager */ |
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#define DFI_SEL_CHK (SOCFPGA_SYSMGR_REG_BASE + DFI_CFG_OFFSET) |
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#endif |
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LOG_MODULE_REGISTER(flash_cdns_nand, CONFIG_FLASH_LOG_LEVEL); |
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struct flash_cadence_nand_data { |
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DEVICE_MMIO_NAMED_RAM(nand_reg); |
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DEVICE_MMIO_NAMED_RAM(sdma); |
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/* device info structure */ |
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struct cadence_nand_params params; |
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/* Mutex to prevent multiple processes from accessing the same driver api */ |
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struct k_mutex nand_mutex; |
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#if CONFIG_CDNS_NAND_INTERRUPT_SUPPORT |
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/* Semaphore to send a signal from an interrupt handler to a thread */ |
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struct k_sem interrupt_sem; |
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#endif |
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}; |
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struct flash_cadence_nand_config { |
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DEVICE_MMIO_NAMED_ROM(nand_reg); |
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DEVICE_MMIO_NAMED_ROM(sdma); |
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#if CDNS_NAND_RESET_SUPPORT |
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/* Reset controller device configuration for NAND*/ |
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const struct reset_dt_spec reset; |
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/* Reset controller device configuration for Combo Phy*/ |
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const struct reset_dt_spec combo_phy_reset; |
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#endif |
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#if CONFIG_CDNS_NAND_INTERRUPT_SUPPORT |
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void (*irq_config)(void); |
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#endif |
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}; |
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static const struct flash_parameters flash_cdns_parameters = {.write_block_size = FLASH_WRITE_SIZE, |
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.erase_value = 0xFF}; |
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#if CONFIG_FLASH_PAGE_LAYOUT |
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struct flash_pages_layout flash_cdns_pages_layout; |
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void flash_cdns_page_layout(const struct device *nand_dev, const struct flash_pages_layout **layout, |
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size_t *layout_size) |
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{ |
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struct flash_cadence_nand_data *const nand_data = DEV_DATA(nand_dev); |
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struct cadence_nand_params *nand_param = &nand_data->params; |
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flash_cdns_pages_layout.pages_count = nand_param->page_count; |
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flash_cdns_pages_layout.pages_size = nand_param->page_size; |
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*layout = &flash_cdns_pages_layout; |
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*layout_size = 1; |
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} |
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#endif |
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static int flash_cdns_nand_erase(const struct device *nand_dev, off_t offset, size_t len) |
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{ |
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struct flash_cadence_nand_data *const nand_data = DEV_DATA(nand_dev); |
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struct cadence_nand_params *nand_param = &nand_data->params; |
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int ret; |
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k_mutex_lock(&nand_data->nand_mutex, K_FOREVER); |
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ret = cdns_nand_erase(nand_param, offset, len); |
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k_mutex_unlock(&nand_data->nand_mutex); |
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return ret; |
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} |
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static int flash_cdns_nand_write(const struct device *nand_dev, off_t offset, const void *data, |
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size_t len) |
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{ |
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struct flash_cadence_nand_data *const nand_data = DEV_DATA(nand_dev); |
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struct cadence_nand_params *nand_param = &nand_data->params; |
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int ret; |
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if (data == NULL) { |
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LOG_ERR("Invalid input parameter for NAND Flash Write!"); |
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return -EINVAL; |
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} |
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k_mutex_lock(&nand_data->nand_mutex, K_FOREVER); |
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ret = cdns_nand_write(nand_param, data, offset, len); |
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k_mutex_unlock(&nand_data->nand_mutex); |
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return ret; |
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} |
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static int flash_cdns_nand_read(const struct device *nand_dev, off_t offset, void *data, size_t len) |
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{ |
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struct flash_cadence_nand_data *const nand_data = DEV_DATA(nand_dev); |
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struct cadence_nand_params *nand_param = &nand_data->params; |
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int ret; |
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if (data == NULL) { |
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LOG_ERR("Invalid input parameter for NAND Flash Read!"); |
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return -EINVAL; |
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} |
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k_mutex_lock(&nand_data->nand_mutex, K_FOREVER); |
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ret = cdns_nand_read(nand_param, data, offset, len); |
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k_mutex_unlock(&nand_data->nand_mutex); |
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return ret; |
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} |
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static const struct flash_parameters *flash_cdns_get_parameters(const struct device *nand_dev) |
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{ |
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ARG_UNUSED(nand_dev); |
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return &flash_cdns_parameters; |
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} |
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static DEVICE_API(flash, flash_cdns_nand_api) = { |
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.erase = flash_cdns_nand_erase, |
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.write = flash_cdns_nand_write, |
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.read = flash_cdns_nand_read, |
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.get_parameters = flash_cdns_get_parameters, |
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#ifdef CONFIG_FLASH_PAGE_LAYOUT |
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.page_layout = flash_cdns_page_layout, |
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#endif |
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}; |
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#if CONFIG_CDNS_NAND_INTERRUPT_SUPPORT |
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static void cdns_nand_irq_handler(const struct device *nand_dev) |
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{ |
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struct flash_cadence_nand_data *const nand_data = DEV_DATA(nand_dev); |
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struct cadence_nand_params *nand_param = &nand_data->params; |
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cdns_nand_irq_handler_ll(nand_param); |
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k_sem_give(&nand_param->interrupt_sem_t); |
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} |
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#endif |
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static int flash_cdns_nand_init(const struct device *nand_dev) |
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{ |
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DEVICE_MMIO_NAMED_MAP(nand_dev, nand_reg, K_MEM_CACHE_NONE); |
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DEVICE_MMIO_NAMED_MAP(nand_dev, sdma, K_MEM_CACHE_NONE); |
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const struct flash_cadence_nand_config *nand_config = DEV_CFG(nand_dev); |
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struct flash_cadence_nand_data *const nand_data = DEV_DATA(nand_dev); |
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struct cadence_nand_params *nand_param = &nand_data->params; |
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int ret; |
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#ifdef CONFIG_BOARD_INTEL_SOCFPGA_AGILEX5_SOCDK |
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uint32_t status; |
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status = sys_read32(DFI_SEL_CHK); |
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if ((status & 1) != 0) { |
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LOG_ERR("DFI not configured for NAND Flash controller!!!"); |
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return -ENODEV; |
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} |
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#endif |
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#if CDNS_NAND_RESET_SUPPORT |
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/* Reset Combo phy and NAND only if reset controller driver is supported */ |
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if ((nand_config->combo_phy_reset.dev != NULL) && (nand_config->reset.dev != NULL)) { |
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if (!device_is_ready(nand_config->reset.dev)) { |
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LOG_ERR("Reset controller device not ready"); |
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return -ENODEV; |
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} |
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ret = reset_line_toggle(nand_config->combo_phy_reset.dev, |
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nand_config->combo_phy_reset.id); |
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if (ret != 0) { |
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LOG_ERR("Combo phy reset failed"); |
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return ret; |
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} |
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ret = reset_line_toggle(nand_config->reset.dev, nand_config->reset.id); |
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if (ret != 0) { |
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LOG_ERR("NAND reset failed"); |
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return ret; |
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} |
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} |
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#endif |
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nand_param->nand_base = DEVICE_MMIO_NAMED_GET(nand_dev, nand_reg); |
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nand_param->sdma_base = DEVICE_MMIO_NAMED_GET(nand_dev, sdma); |
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ret = k_mutex_init(&nand_data->nand_mutex); |
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if (ret != 0) { |
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LOG_ERR("Mutex creation Failed"); |
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return ret; |
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} |
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#if CONFIG_CDNS_NAND_INTERRUPT_SUPPORT |
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if (nand_config->irq_config == NULL) { |
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LOG_ERR("Interrupt function not initialized!!"); |
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return -EINVAL; |
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} |
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nand_config->irq_config(); |
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ret = k_sem_init(&nand_param->interrupt_sem_t, 0, 1); |
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if (ret != 0) { |
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LOG_ERR("Semaphore creation Failed"); |
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return ret; |
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} |
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#endif |
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nand_param->page_count = |
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(nand_param->npages_per_block * nand_param->nblocks_per_lun * nand_param->nluns); |
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/* NAND Memory Controller init */ |
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ret = cdns_nand_init(nand_param); |
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if (ret != 0) { |
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LOG_ERR("NAND initialization Failed"); |
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return ret; |
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} |
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return 0; |
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} |
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#define CDNS_NAND_RESET_SPEC_INIT(inst) \ |
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.reset = RESET_DT_SPEC_INST_GET_BY_IDX(inst, 0), \ |
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.combo_phy_reset = RESET_DT_SPEC_INST_GET_BY_IDX(inst, 1), |
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#define CREATE_FLASH_CADENCE_NAND_DEVICE(inst) \ |
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IF_ENABLED(CONFIG_CDNS_NAND_INTERRUPT_SUPPORT, \ |
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(static void cdns_nand_irq_config_##inst(void);)) \ |
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struct flash_cadence_nand_data flash_cadence_nand_data_##inst = { \ |
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.params = { \ |
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.datarate_mode = DT_INST_PROP(inst, data_rate_mode), \ |
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}}; \ |
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const struct flash_cadence_nand_config flash_cadence_nand_config_##inst = { \ |
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DEVICE_MMIO_NAMED_ROM_INIT_BY_NAME(nand_reg, DT_DRV_INST(inst)), \ |
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DEVICE_MMIO_NAMED_ROM_INIT_BY_NAME(sdma, DT_DRV_INST(inst)), \ |
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IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, resets), (CDNS_NAND_RESET_SPEC_INIT(inst))) \ |
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IF_ENABLED(CONFIG_CDNS_NAND_INTERRUPT_SUPPORT, \ |
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(.irq_config = cdns_nand_irq_config_##inst,))}; \ |
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DEVICE_DT_INST_DEFINE(inst, flash_cdns_nand_init, NULL, &flash_cadence_nand_data_##inst, \ |
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&flash_cadence_nand_config_##inst, POST_KERNEL, \ |
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CONFIG_FLASH_INIT_PRIORITY, &flash_cdns_nand_api); \ |
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IF_ENABLED(CONFIG_CDNS_NAND_INTERRUPT_SUPPORT, \ |
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(static void cdns_nand_irq_config_##inst(void) \ |
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{ \ |
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IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), \ |
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cdns_nand_irq_handler, DEVICE_DT_INST_GET(inst), 0); \ |
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irq_enable(DT_INST_IRQN(inst)); \ |
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})) |
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DT_INST_FOREACH_STATUS_OKAY(CREATE_FLASH_CADENCE_NAND_DEVICE)
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