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378 lines
10 KiB
378 lines
10 KiB
#ifndef PHY_CYCLONEV_SRC |
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#define PHY_CYCLONEV_SRC |
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/* |
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* SPDX-License-Identifier: Apache-2.0 |
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* Copyright (C) 2022, Intel Corporation |
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* Description: |
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* Driver for the PHY KSZ9021RL/RN Datasheet:(https://ww1.microchip.com/ |
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* downloads/en/DeviceDoc/KSZ9021RL-RN-Data-Sheet-DS00003050A.pdf) |
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* specifically designed for Cyclone V SoC DevKit use only. |
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*/ |
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/* PHY */ |
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/* According to default Cyclone V DevKit Bootstrap Encoding Scheme */ |
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#include "eth_cyclonev_priv.h" |
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#include <stdio.h> |
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#include <zephyr/kernel.h> |
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#include <sys/types.h> |
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#define PHY_ADDR (4) |
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/* PHY_Read_write_Timeouts */ |
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#define PHY_READ_TO ((uint32_t)0x0004FFFF) |
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#define PHY_WRITE_TO ((uint32_t)0x0004FFFF) |
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/* Speed and Duplex mask values */ |
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#define PHY_SPEED_100 (0x0020) |
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#define PHY_SPEED_1000 (0x0040) |
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#define PHY_CLK_AND_CONTROL_PAD_SKEW_VALUE 0xa0d0 |
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#define PHY_RX_DATA_PAD_SKEW_VALUE 0x0000 |
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/* Write/read to/from extended registers */ |
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#define MII_KSZPHY_EXTREG 0x0b |
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#define KSZPHY_EXTREG_WRITE 0x8000 |
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#define MII_KSZPHY_EXTREG_WRITE 0x0c |
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#define MII_KSZPHY_EXTREG_READ 0x0d |
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/* PHY Regs */ |
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/* Basic Control Register */ |
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#define PHY_BCR (0) |
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#define PHY_RESET BIT(15) /* Do a PHY reset */ |
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#define PHY_AUTONEGOTIATION BIT(12) |
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#define PHY_RESTART_AUTONEGOTIATION BIT(9) |
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/* Basic Status Register */ |
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#define PHY_BSR BIT(0) |
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#define PHY_AUTOCAP BIT(3) /* Auto-negotiation capability */ |
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#define PHY_LINKED_STATUS BIT(2) |
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#define PHY_AUTONEGO_COMPLETE BIT(5) |
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/* Auto-Negotiation Advertisement */ |
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#define PHY_AUTON (4) |
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#define PHYANA_10BASET BIT(5) |
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#define PHYANA_10BASETFD BIT(6) |
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#define PHYANA_100BASETX BIT(7) |
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#define PHYANA_100BASETXFD BIT(8) |
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#define PHYSYMETRIC_PAUSE BIT(10) |
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#define PHYASYMETRIC_PAUSE BIT(11) |
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/* 1000Base-T Control */ |
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#define PHY_1GCTL (9) |
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#define PHYADVERTISE_1000HALF BIT(8) |
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#define PHYADVERTISE_1000FULL BIT(9) |
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#define PHYINDICATE_PORTTYPE BIT(10) |
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#define PHYCONFIG_MASTER BIT(11) |
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#define PHYENABLE_MANUALCONFIG BIT(12) |
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/* PHY Control Register */ |
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#define PHY_CR (31) |
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#define PHY_DUPLEX_STATUS BIT(3) |
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/* Extended registers */ |
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#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 |
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#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 |
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#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 |
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int alt_eth_phy_write_register(uint16_t emac_instance, uint16_t phy_reg, |
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uint16_t phy_value, struct eth_cyclonev_priv *p); |
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int alt_eth_phy_read_register(uint16_t emac_instance, uint16_t phy_reg, |
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uint16_t *rdval, struct eth_cyclonev_priv *p); |
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int alt_eth_phy_write_register_extended(uint16_t emac_instance, uint16_t phy_reg, |
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uint16_t phy_value, struct eth_cyclonev_priv *p); |
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int alt_eth_phy_read_register_extended(uint16_t emac_instance, uint16_t phy_reg, |
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uint16_t *rdval, struct eth_cyclonev_priv *p); |
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int alt_eth_phy_config(uint16_t instance, struct eth_cyclonev_priv *p); |
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int alt_eth_phy_reset(uint16_t instance, struct eth_cyclonev_priv *p); |
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int alt_eth_phy_get_duplex_and_speed(uint16_t *phy_duplex_status, uint16_t *phy_speed, |
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uint16_t instance, struct eth_cyclonev_priv *p); |
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int alt_eth_phy_write_register(uint16_t emac_instance, uint16_t phy_reg, |
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uint16_t phy_value, struct eth_cyclonev_priv *p) |
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{ |
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uint16_t tmpreg = 0; |
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volatile uint32_t timeout = 0; |
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uint16_t phy_addr; |
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if (emac_instance > 1) { |
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return -1; |
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} |
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phy_addr = PHY_ADDR; |
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/* Prepare the MII address register value */ |
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tmpreg = 0; |
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/* Set the PHY device address */ |
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tmpreg |= EMAC_GMAC_GMII_ADDR_PA_SET(phy_addr); |
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/* Set the PHY register address */ |
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tmpreg |= EMAC_GMAC_GMII_ADDR_GR_SET(phy_reg); |
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/* Set the write mode */ |
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tmpreg |= EMAC_GMAC_GMII_ADDR_GW_SET_MSK; |
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/* Set the clock divider */ |
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tmpreg |= EMAC_GMAC_GMII_ADDR_CR_SET(EMAC_GMAC_GMII_ADDR_CR_E_DIV102); |
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/* Set the MII Busy bit */ |
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tmpreg |= EMAC_GMAC_GMII_ADDR_GB_SET(EMAC_GMAC_GMII_ADDR_GB_SET_MSK); |
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/* Give the value to the MII data register */ |
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sys_write32(phy_value & 0xffff, EMAC_GMAC_GMII_DATA_ADDR(p->base_addr)); |
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/* Write the result value into the MII Address register */ |
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sys_write32(tmpreg & 0xffff, EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr)); |
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/* Check the Busy flag */ |
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do { |
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timeout++; |
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tmpreg = sys_read32(EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr)); |
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} while ((tmpreg & EMAC_GMAC_GMII_ADDR_GB_SET_MSK) && (timeout < PHY_WRITE_TO)); |
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/* Return ERROR in case of timeout */ |
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if (timeout == PHY_WRITE_TO) { |
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return -1; |
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} |
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/* Return SUCCESS */ |
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return 0; |
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} |
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int alt_eth_phy_read_register(uint16_t emac_instance, uint16_t phy_reg, uint16_t *rdval, |
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struct eth_cyclonev_priv *p) |
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{ |
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uint16_t tmpreg = 0; |
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volatile uint32_t timeout = 0; |
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uint16_t phy_addr; |
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if (emac_instance > 1) { |
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return -1; |
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} |
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phy_addr = PHY_ADDR; |
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/* Prepare the MII address register value */ |
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tmpreg = 0; |
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/* Set the PHY device address */ |
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tmpreg |= EMAC_GMAC_GMII_ADDR_PA_SET(phy_addr); |
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/* Set the PHY register address */ |
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tmpreg |= EMAC_GMAC_GMII_ADDR_GR_SET(phy_reg); |
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/* Set the read mode */ |
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tmpreg &= EMAC_GMAC_GMII_ADDR_GW_CLR_MSK; |
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/* Set the clock divider */ |
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tmpreg |= EMAC_GMAC_GMII_ADDR_CR_SET(EMAC_GMAC_GMII_ADDR_CR_E_DIV102); |
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/* Set the MII Busy bit */ |
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tmpreg |= EMAC_GMAC_GMII_ADDR_GB_SET(EMAC_GMAC_GMII_ADDR_GB_SET_MSK); |
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/* Write the result value into the MII Address register */ |
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sys_write32(tmpreg & 0xffff, EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr)); |
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/* Check the Busy flag */ |
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do { |
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timeout++; |
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tmpreg = sys_read32(EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr)); |
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} while ((tmpreg & EMAC_GMAC_GMII_ADDR_GB_SET_MSK) && (timeout < PHY_READ_TO)); |
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/* Return ERROR in case of timeout */ |
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if (timeout == PHY_READ_TO) { |
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return -1; |
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} |
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/* Return data register value */ |
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*rdval = sys_read32(EMAC_GMAC_GMII_DATA_ADDR(p->base_addr)); |
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return 0; |
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} |
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int alt_eth_phy_write_register_extended(uint16_t emac_instance, uint16_t phy_reg, |
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uint16_t phy_value, struct eth_cyclonev_priv *p) |
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{ |
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int rc; |
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rc = alt_eth_phy_write_register(emac_instance, MII_KSZPHY_EXTREG, |
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KSZPHY_EXTREG_WRITE | phy_reg, p); |
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if (rc == -1) { |
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return rc; |
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} |
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rc = alt_eth_phy_write_register(emac_instance, MII_KSZPHY_EXTREG_WRITE, phy_value, p); |
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return rc; |
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} |
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int alt_eth_phy_read_register_extended(uint16_t emac_instance, uint16_t phy_reg, uint16_t *rdval, |
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struct eth_cyclonev_priv *p) |
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{ |
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int rc; |
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rc = alt_eth_phy_write_register(emac_instance, MII_KSZPHY_EXTREG, phy_reg, p); |
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if (rc == -1) { |
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return rc; |
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} |
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k_sleep(K_MSEC(1)); |
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rc = alt_eth_phy_read_register(emac_instance, MII_KSZPHY_EXTREG_READ, rdval, p); |
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return rc; |
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} |
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int alt_eth_phy_config(uint16_t instance, struct eth_cyclonev_priv *p) |
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{ |
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int rc; |
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uint16_t rdval; |
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uint32_t timeout; |
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/*-------------------- Configure the PHY skew values ----------------*/ |
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rc = alt_eth_phy_write_register_extended(instance, MII_KSZPHY_CLK_CONTROL_PAD_SKEW, |
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PHY_CLK_AND_CONTROL_PAD_SKEW_VALUE, p); |
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if (rc == -1) { |
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return rc; |
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} |
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rc = alt_eth_phy_write_register_extended(instance, MII_KSZPHY_RX_DATA_PAD_SKEW, |
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PHY_RX_DATA_PAD_SKEW_VALUE, p); |
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if (rc == -1) { |
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return rc; |
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} |
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/* Implement Auto-negotiation Process */ |
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/* Check PHY Status if auto-negotiation is supported */ |
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rc = alt_eth_phy_read_register(instance, PHY_BSR, &rdval, p); |
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if (((rdval & PHY_AUTOCAP) == 0) || (rc == -1)) { |
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return -1; |
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} |
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/* Set Advertise capabilities for 10Base-T/ |
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*10Base-T full-duplex/100Base-T/100Base-T full-duplex |
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*/ |
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rc = alt_eth_phy_read_register(instance, PHY_AUTON, &rdval, p); |
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if (rc == -1) { |
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return rc; |
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} |
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rdval |= (PHYANA_10BASET | PHYANA_10BASETFD | PHYANA_100BASETX | PHYANA_100BASETXFD | |
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PHYSYMETRIC_PAUSE); |
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rc = alt_eth_phy_write_register(instance, PHY_AUTON, rdval, p); |
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if (rc == -1) { |
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return rc; |
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} |
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/* Set Advertise capabilities for 1000 Base-T/1000 Base-T full-duplex */ |
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rc = alt_eth_phy_write_register(instance, PHY_1GCTL, |
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PHYADVERTISE_1000FULL | PHYADVERTISE_1000HALF | |
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PHYINDICATE_PORTTYPE | PHYCONFIG_MASTER | PHYENABLE_MANUALCONFIG |
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, p); |
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if (rc == -1) { |
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return rc; |
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} |
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/* Wait for linked status... */ |
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timeout = 0; |
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do { |
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timeout++; |
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rc = alt_eth_phy_read_register(instance, PHY_BSR, &rdval, p); |
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} while (!(rdval & PHY_LINKED_STATUS) && (timeout < PHY_READ_TO) && (rc == 0)); |
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/* Return ERROR in case of timeout */ |
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if ((timeout == PHY_READ_TO) || (rc == -1)) { |
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LOG_ERR("Error Link Down\n"); |
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return -1; |
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} |
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LOG_INF("Link is up!"); |
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/* Configure the PHY for AutoNegotiate */ |
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rc = alt_eth_phy_read_register(instance, PHY_BCR, &rdval, p); |
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if (rc == -1) { |
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return rc; |
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} |
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rdval |= PHY_AUTONEGOTIATION; |
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rdval |= PHY_RESTART_AUTONEGOTIATION; |
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rc = alt_eth_phy_write_register(instance, PHY_BCR, rdval, p); |
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if (rc == -1) { |
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return rc; |
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} |
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/* Wait until the auto-negotiation is completed */ |
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timeout = 0; |
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do { |
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timeout++; |
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rc = alt_eth_phy_read_register(instance, PHY_BSR, &rdval, p); |
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} while (!(rdval & PHY_AUTONEGO_COMPLETE) && (timeout < PHY_READ_TO) && (rc == 0)); |
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/* Return ERROR in case of timeout */ |
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if ((timeout == PHY_READ_TO) || (rc == -1)) { |
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alt_eth_phy_read_register(instance, PHY_BSR, &rdval, p); |
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LOG_ERR("Auto Negotiation: Status reg = 0x%x\n", rdval); |
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return -1; |
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} |
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LOG_INF("Auto Negotiation Complete!"); |
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return rc; |
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}; |
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int alt_eth_phy_reset(uint16_t instance, struct eth_cyclonev_priv *p) |
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{ |
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int i; |
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int rc; |
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uint16_t rdval; |
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/* Put the PHY in reset mode */ |
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if ((alt_eth_phy_write_register(instance, PHY_BCR, PHY_RESET, p)) != 0) { |
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/* Return ERROR in case of write timeout */ |
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return -1; |
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} |
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/* Wait for the reset to clear */ |
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for (i = 0; i < 10; i++) { |
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k_sleep(K_MSEC(10)); |
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rc = alt_eth_phy_read_register(instance, PHY_BCR, &rdval, p); |
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if (((rdval & PHY_RESET) == 0) || (rc == -1)) { |
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break; |
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} |
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} |
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if (i == 10) { |
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return -1; |
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} |
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/* Delay to assure PHY reset */ |
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k_sleep(K_MSEC(10)); |
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return rc; |
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}; |
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int alt_eth_phy_get_duplex_and_speed(uint16_t *phy_duplex_status, uint16_t *phy_speed, |
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uint16_t instance, struct eth_cyclonev_priv *p) |
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{ |
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LOG_DBG("PHY: func_alt_eth_phy_get_duplex_and_speed\n"); |
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uint16_t regval = 0; |
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int rc; |
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rc = alt_eth_phy_read_register(instance, PHY_CR, ®val, p); |
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if (regval & PHY_DUPLEX_STATUS) { |
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*phy_duplex_status = 1; |
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} else { |
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*phy_duplex_status = 0; |
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} |
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if (regval & PHY_SPEED_100) { |
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*phy_speed = 100; |
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} else { |
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if (regval & PHY_SPEED_1000) { |
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*phy_speed = 1000; |
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} else { |
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*phy_speed = 10; |
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} |
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} |
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return rc; |
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} |
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#endif
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