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266 lines
8.7 KiB
266 lines
8.7 KiB
/* |
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* Copyright (c) 2023 PHOENIX CONTACT Electronics GmbH |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#ifndef ETH_ADIN2111_PRIV_H__ |
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#define ETH_ADIN2111_PRIV_H__ |
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#include <stdint.h> |
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#include <stdbool.h> |
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#include <zephyr/kernel.h> |
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#include <zephyr/drivers/gpio.h> |
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#include <zephyr/drivers/spi.h> |
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#include <zephyr/net/net_if.h> |
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#include <ethernet/eth_stats.h> |
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/* SPI frequency maximum, based on clock cycle time */ |
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#define ADIN2111_SPI_MAX_FREQUENCY 25000000U |
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#define ADIN2111_PHYID 0x01U |
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/* PHY Identification Register Reset Value */ |
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#define ADIN2111_PHYID_RST_VAL 0x0283BCA1U |
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#define ADIN1110_PHYID_RST_VAL 0x0283BC91U |
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/* Reset Control and Status Register */ |
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#define ADIN2111_RESET 0x03U |
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/* MACPHY software reset */ |
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#define ADIN2111_RESET_SWRESET BIT(0) |
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/* Configuration Register 0 */ |
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#define ADIN2111_CONFIG0 0x04U |
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/* Configuration Synchronization */ |
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#define ADIN2111_CONFIG0_SYNC BIT(15) |
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/* Transmit Frame Check Sequence Validation Enable */ |
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#define ADIN2111_CONFIG0_TXFCSVE BIT(14) |
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/* Zero Align Receive Frame Enable */ |
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#define ADIN2111_CONFIG0_ZARFE BIT(12) |
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/* New packet received only after a new CS assertion */ |
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#define ADIN2111_CONFIG0_CSARFE BIT(13) |
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/* Transmit Cut Through Enable */ |
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#define ADIN2111_CONFIG0_TXCTE BIT(9) |
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/* Receive Cut Through Enable. Must be 0 for Generic SPI */ |
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#define ADIN2111_CONFIG0_RXCTE BIT(8) |
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/* Configuration Register 2 */ |
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#define ADIN2111_CONFIG2 0x06U |
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/* Forward Frames from Port 2 Not Matching a MAC Address to Port 1 */ |
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#define ADIN2111_CONFIG2_P2_FWD_UNK2P1 BIT(14) |
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/* Forward Frames from Port 1 Not Matching a MAC Address to Port 2 */ |
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#define ADIN2111_CONFIG2_P1_FWD_UNK2P2 BIT(13) |
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/* Forward Frames Not Matching Any MAC Address to the Host */ |
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#define ADIN2111_CONFIG2_P2_FWD_UNK2HOST BIT(12) |
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/* Enable Cut Through from Port to Port */ |
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#define ADIN2111_CONFIG2_PORT_CUT_THRU_EN BIT(11) |
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/* Enable CRC Append */ |
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#define ADIN2111_CONFIG2_CRC_APPEND BIT(5) |
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/* Forward Frames Not Matching Any MAC Address to the Host */ |
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#define ADIN2111_CONFIG2_P1_FWD_UNK2HOST BIT(2) |
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/* Status Register 0 */ |
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#define ADIN2111_STATUS0 0x08U |
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/* PHY Interrupt for Port 1 */ |
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#define ADIN2111_STATUS0_PHYINT BIT(7) |
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/** |
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* Reset Complete. |
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* The bit is set when the MACPHY reset is complete |
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* and ready for configuration. |
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*/ |
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#define ADIN2111_STATUS0_RESETC BIT(6) |
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/* Value to completely clear status register 0 */ |
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#define ADIN2111_STATUS0_CLEAR 0x1F7FU |
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/* Status Register 1 */ |
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#define ADIN2111_STATUS1 0x09U |
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/* PHY Interrupt for Port 2 */ |
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#define ADIN2111_STATUS1_PHYINT BIT(19) |
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/* Port 2 RX FIFO Contains Data */ |
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#define ADIN2111_STATUS1_P2_RX_RDY BIT(17) |
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/* Indicates that a CRC error was detected */ |
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#define ADIN2111_STATUS1_SPI_ERR BIT(10) |
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/* Port 1 RX FIFO Contains Data */ |
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#define ADIN2111_STATUS1_P1_RX_RDY BIT(4) |
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/* Frame transmitted */ |
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#define ADIN2111_STATUS1_TX_RDY BIT(3) |
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/* Value to completely clear status register 1 */ |
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#define ADIN2111_STATUS1_CLEAR 0xFFF01F08U |
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/* Buffer Status Register */ |
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#define ADIN2111_BUFSTS 0x0BU |
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/* Rx chunks available */ |
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#define ADIN2111_BUFSTS_RCA_MASK GENMASK(7, 0) |
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/* Tx credits */ |
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#define ADIN2111_BUFSTS_TXC 8U |
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#define ADIN2111_BUFSTS_TXC_MASK GENMASK(15, 8) |
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/* Interrupt Mask Register 0 */ |
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#define ADIN2111_IMASK0 0x0CU |
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/* Physical Layer Interrupt Mask */ |
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#define ADIN2111_IMASK0_PHYINTM BIT(7) |
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/* Interrupt Mask Register 1 */ |
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#define ADIN2111_IMASK1 0x0DU |
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/* Mask Bit for P2_PHYINT */ |
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#define ADIN2111_IMASK1_P2_PHYINT_MASK BIT(19) |
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/*!< Mask Bit for P2_RX_RDY. Generic SPI only.*/ |
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#define ADIN2111_IMASK1_P2_RX_RDY_MASK BIT(17) |
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/*!< Mask Bit for SPI_ERR. Generic SPI only. */ |
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#define ADIN2111_IMASK1_SPI_ERR_MASK BIT(10) |
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/*!< Mask Bit for P1_RX_RDY. Generic SPI only.*/ |
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#define ADIN2111_IMASK1_P1_RX_RDY_MASK BIT(4) |
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/*!< Mask Bit for TX_FRM_DONE. Generic SPI only.*/ |
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#define ADIN2111_IMASK1_TX_RDY_MASK BIT(3) |
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/* MAC Tx Frame Size Register */ |
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#define ADIN2111_TX_FSIZE 0x30U |
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/* Tx FIFO Space Register */ |
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#define ADIN2111_TX_SPACE 0x32U |
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/* MAC Address Rule and DA Filter Upper 16 Bits Registers */ |
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#define ADIN2111_ADDR_FILT_UPR 0x50U |
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#define ADIN2111_ADDR_APPLY2PORT2 BIT(31) |
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#define ADIN2111_ADDR_APPLY2PORT1 BIT(30) |
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#define ADIN2111_ADDR_TO_OTHER_PORT BIT(17) |
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#define ADIN2111_ADDR_TO_HOST BIT(16) |
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/* MAC Address DA Filter Lower 32 Bits Registers */ |
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#define ADIN2111_ADDR_FILT_LWR 0x51U |
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/* Upper 16 Bits of the MAC Address Mask */ |
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#define ADIN2111_ADDR_MSK_UPR 0x70U |
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/* Lower 32 Bits of the MAC Address Mask */ |
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#define ADIN2111_ADDR_MSK_LWR 0x71U |
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/* P1 MAC Rx Frame Size Register */ |
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#define ADIN2111_P1_RX_FSIZE 0x90U |
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/* P1 MAC Receive Register */ |
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#define ADIN2111_P1_RX 0x91U |
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/* P2 MAC Rx Frame Size Register */ |
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#define ADIN2111_P2_RX_FSIZE 0xC0U |
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/* P2 MAC Receive Register */ |
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#define ADIN2111_P2_RX 0xC1U |
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/* MAC reset status */ |
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#define ADIN1110_MAC_RST_STATUS_REG 0x3BU |
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/* MAC reset */ |
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#define ADIN2111_SOFT_RST_REG 0x3CU |
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#define ADIN2111_SWRESET_KEY1 0x4F1CU |
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#define ADIN2111_SWRESET_KEY2 0xC1F4U |
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#define ADIN2111_SWRELEASE_KEY1 0x6F1AU |
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#define ADIN2111_SWRELEASE_KEY2 0xA1F6U |
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/* SPI header size in bytes */ |
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#define ADIN2111_SPI_HEADER_SIZE 2U |
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/* SPI header size for write transaction */ |
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#define ADIN2111_WRITE_HEADER_SIZE ADIN2111_SPI_HEADER_SIZE |
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/* SPI header size for read transaction (1 for TA) */ |
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#define ADIN2111_READ_HEADER_SIZE (ADIN2111_SPI_HEADER_SIZE + 1U) |
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/* SPI register write buffer size without CRC */ |
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#define ADIN2111_REG_WRITE_BUF_SIZE (ADIN2111_WRITE_HEADER_SIZE + sizeof(uint32_t)) |
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/* SPI register write buffer with appended CRC size (1 for header, 1 for register) */ |
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#define ADIN2111_REG_WRITE_BUF_SIZE_CRC (ADIN2111_REG_WRITE_BUF_SIZE + 2U) |
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/* SPI register read buffer size with TA without CRC */ |
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#define ADIN2111_REG_READ_BUF_SIZE (ADIN2111_READ_HEADER_SIZE + sizeof(uint32_t)) |
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/* SPI register read buffer with TA and appended CRC size (1 header, 1 for register) */ |
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#define ADIN2111_REG_READ_BUF_SIZE_CRC (ADIN2111_REG_READ_BUF_SIZE + 2U) |
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/* SPI read fifo cmd buffer size with TA without CRC */ |
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#define ADIN2111_FIFO_READ_CMD_BUF_SIZE (ADIN2111_READ_HEADER_SIZE) |
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/* SPI read fifo cmd buffer with TA and appended CRC size */ |
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#define ADIN2111_FIFO_READ_CMD_BUF_SIZE_CRC (ADIN2111_FIFO_READ_CMD_BUF_SIZE + 1U) |
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/* SPI Header for writing control transaction in half duplex mode */ |
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#define ADIN2111_WRITE_TXN_CTRL 0xA000U |
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/* SPI Header for writing control transaction with MAC TX register (!) in half duplex mode */ |
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#define ADIN2111_TXN_CTRL_TX_REG 0xA031U |
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/* SPI Header for reading control transaction in half duplex mode */ |
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#define ADIN2111_READ_TXN_CTRL 0x8000U |
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/* Frame header size in bytes */ |
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#define ADIN2111_FRAME_HEADER_SIZE 2U |
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#define ADIN2111_INTERNAL_HEADER_SIZE 2U |
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/* Number of buffer bytes in TxFIFO to provide frame margin upon writes */ |
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#define ADIN2111_TX_FIFO_BUFFER_MARGIN 4U |
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/* Manufacturer unique ID */ |
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#define ADIN2111_PHYID_OUI 0xa0ef |
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/* Open Alliance definitions */ |
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#define ADIN2111_OA_ALLOC_TIMEOUT K_MSEC(10) |
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/* Max setting to a max RCA of 255 68-bytes ckunks */ |
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#define ADIN2111_OA_BUF_SZ (255U * 64U) |
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#define ADIN2111_OA_CTL_LEN_PROT 16U |
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#define ADIN2111_OA_CTL_LEN 12U |
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#define ADIN2111_OA_CTL_MMS BIT(24) |
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#define ADIN2111_OA_CTL_WNR BIT(29) |
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#define ADIN2111_OA_DATA_HDR_DNC BIT(31) |
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#define ADIN2111_OA_DATA_HDR_NORX BIT(29) |
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#define ADIN2111_OA_DATA_HDR_VS 22U |
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#define ADIN2111_OA_DATA_HDR_DV BIT(21) |
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#define ADIN2111_OA_DATA_HDR_SV BIT(20) |
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#define ADIN2111_OA_DATA_HDR_EV BIT(14) |
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#define ADIN2111_OA_DATA_HDR_EBO 8U |
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#define ADIN2111_OA_DATA_FTR_SYNC BIT(29) |
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#define ADIN2111_OA_DATA_FTR_EBO 8U |
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#define ADIN2111_OA_DATA_FTR_DV BIT(21) |
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#define ADIN2111_OA_DATA_FTR_SV BIT(20) |
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#define ADIN2111_OA_DATA_FTR_EV BIT(14) |
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#define ADIN2111_OA_DATA_FTR_SWO 16U |
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#define ADIN2111_OA_DATA_FTR_SWO_MSK GENMASK(19, 16) |
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#define ADIN2111_OA_DATA_FTR_EBO 8U |
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#define ADIN2111_OA_DATA_FTR_EBO_MSK GENMASK(13, 8) |
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enum adin2111_chips_id { |
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ADIN2111_MAC = 0, |
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ADIN1110_MAC, |
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}; |
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struct adin2111_config { |
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enum adin2111_chips_id id; |
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struct spi_dt_spec spi; |
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struct gpio_dt_spec interrupt; |
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struct gpio_dt_spec reset; |
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}; |
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struct adin2111_data { |
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struct k_mutex lock; |
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struct k_sem offload_sem; |
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uint32_t imask0; |
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uint32_t imask1; |
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uint8_t *buf; |
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/* Port 0: PHY 1, Port 1: PHY 2 */ |
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const struct device *port[2]; |
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uint8_t *oa_tx_buf; |
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uint8_t *oa_rx_buf; |
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uint16_t ifaces_left_to_init; |
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uint16_t scur; |
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struct gpio_callback gpio_int_callback; |
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bool oa; |
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bool oa_prot; |
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uint8_t oa_cps; |
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K_KERNEL_STACK_MEMBER(rx_thread_stack, CONFIG_ETH_ADIN2111_IRQ_THREAD_STACK_SIZE); |
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struct k_thread rx_thread; |
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}; |
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struct adin2111_port_data { |
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struct net_if *iface; |
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uint8_t mac_addr[6]; |
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#if defined(CONFIG_NET_STATISTICS_ETHERNET) |
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struct net_stats_eth stats; |
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#endif /* CONFIG_NET_STATISTICS_ETHERNET */ |
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}; |
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struct adin2111_port_config { |
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const struct device *adin; |
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const struct device *phy; |
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const uint16_t port_idx; |
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const uint16_t phy_addr; |
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}; |
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#endif /* ETH_ADIN2111_PRIV_H__ */
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