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150 lines
3.5 KiB
150 lines
3.5 KiB
/* |
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* Copyright (c) 2020 PHYTEC Messtechnik GmbH |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#ifndef ZEPHYR_DRIVERS_DISPLAY_UC81XX_REGS_H_ |
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#define ZEPHYR_DRIVERS_DISPLAY_UC81XX_REGS_H_ |
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/* UC8176/UC8179 */ |
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#define UC81XX_CMD_PSR 0x00 |
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#define UC81XX_CMD_PWR 0x01 |
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#define UC81XX_CMD_POF 0x02 |
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#define UC81XX_CMD_PFS 0x03 |
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#define UC81XX_CMD_PON 0x04 |
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#define UC81XX_CMD_PMES 0x05 |
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#define UC81XX_CMD_BTST 0x06 |
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#define UC81XX_CMD_DSLP 0x07 |
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#define UC81XX_CMD_DTM1 0x10 |
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#define UC81XX_CMD_DSP 0x11 |
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#define UC81XX_CMD_DRF 0x12 |
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/* UC8179 only */ |
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#define UC81XX_CMD_DTM2 0x13 |
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#define UC81XX_CMD_DUSPI 0x15 |
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#define UC81XX_CMD_AUTO 0x17 |
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#define UC81XX_CMD_LUTOPT 0x2A |
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#define UC81XX_CMD_KWOPT 0x2B |
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#define UC81XX_CMD_LUTC 0x20 |
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#define UC81XX_CMD_LUTWW 0x21 |
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#define UC81XX_CMD_LUTKW 0x22 |
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#define UC81XX_CMD_LUTWK 0x23 |
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#define UC81XX_CMD_LUTKK 0x24 |
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#define UC81XX_CMD_LUTBD 0x25 |
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/* UC8176/UC8179 */ |
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#define UC81XX_CMD_PLL 0x30 |
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#define UC81XX_CMD_TSC 0x40 |
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#define UC81XX_CMD_TSE 0x41 |
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#define UC81XX_CMD_TSW 0x42 |
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#define UC81XX_CMD_TSR 0x43 |
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/* UC8179 */ |
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#define UC81XX_CMD_PBC 0x44 |
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/* UC8176/UC8179 - different register layouts */ |
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#define UC81XX_CMD_CDI 0x50 |
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/* UC8176/UC8179 */ |
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#define UC81XX_CMD_LPD 0x51 |
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/* UC8179 */ |
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#define UC81XX_CMD_EVS 0x52 |
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/* UC8176/UC8179 */ |
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#define UC81XX_CMD_TCON 0x60 |
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#define UC81XX_CMD_TRES 0x61 |
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#define UC81XX_CMD_GSST 0x65 |
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#define UC81XX_CMD_REV 0x70 |
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#define UC81XX_CMD_FLG 0x71 |
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#define UC81XX_CMD_AMV 0x80 |
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#define UC81XX_CMD_VV 0x81 |
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#define UC81XX_CMD_VDCS 0x82 |
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#define UC81XX_CMD_PTL 0x90 |
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#define UC81XX_CMD_PTIN 0x91 |
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#define UC81XX_CMD_PTOUT 0x92 |
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#define UC81XX_CMD_PGM 0xA0 |
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#define UC81XX_CMD_APG 0xA1 |
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#define UC81XX_CMD_ROTP 0xA2 |
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#define UC81XX_CMD_CCSET 0xE0 |
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#define UC81XX_CMD_PWS 0xE3 |
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/* UC8179 */ |
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#define UC81XX_CMD_LVSEL 0xE4 |
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/* UC8176/UC8179 */ |
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#define UC81XX_CMD_TSSET 0xE5 |
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/* UC8179 */ |
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#define UC81XX_CMD_TSBDRY 0xE7 |
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#define UC81XX_PSR_REG BIT(5) |
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#define UC81XX_PSR_KW_R BIT(4) |
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#define UC81XX_PSR_UD BIT(3) |
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#define UC81XX_PSR_SHL BIT(2) |
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#define UC81XX_PSR_SHD BIT(1) |
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#define UC81XX_PSR_RST BIT(0) |
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#define UC81XX_AUTO_PON_DRF_POF 0xA5 |
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#define UC81XX_AUTO_PON_DRF_POF_DSLP 0xA7 |
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#define UC8176_CDI_VBD_MASK 0xc0 |
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#define UC8176_CDI_VBD0 BIT(6) |
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#define UC8176_CDI_VBD1 BIT(7) |
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#define UC8176_CDI_DDX1 BIT(5) |
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#define UC8176_CDI_DDX0 BIT(4) |
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#define UC8176_CDI_CDI_MASK 0x0f |
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#define UC8179_CDI_REG_LENGTH 2U |
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#define UC8179_CDI_BDZ_DDX_IDX 0 |
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#define UC8179_CDI_CDI_IDX 1 |
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#define UC8179_CDI_BDZ BIT(7) |
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#define UC8179_CDI_BDV1 BIT(5) |
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#define UC8179_CDI_BDV0 BIT(4) |
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#define UC8179_CDI_N2OCP BIT(3) |
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#define UC8179_CDI_DDX1 BIT(1) |
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#define UC8179_CDI_DDX0 BIT(0) |
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struct uc81xx_tres8 { |
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uint8_t hres; |
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uint8_t vres; |
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} __packed; |
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BUILD_ASSERT(sizeof(struct uc81xx_tres8) == 2); |
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struct uc81xx_ptl8 { |
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uint8_t hrst; |
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uint8_t hred; |
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uint8_t vrst; |
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uint8_t vred; |
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uint8_t flags; |
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} __packed; |
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BUILD_ASSERT(sizeof(struct uc81xx_ptl8) == 5); |
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struct uc81xx_tres16 { |
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uint16_t hres; |
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uint16_t vres; |
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} __packed; |
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BUILD_ASSERT(sizeof(struct uc81xx_tres16) == 4); |
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struct uc81xx_ptl16 { |
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uint16_t hrst; |
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uint16_t hred; |
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uint16_t vrst; |
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uint16_t vred; |
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uint8_t flags; |
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} __packed; |
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BUILD_ASSERT(sizeof(struct uc81xx_ptl16) == 9); |
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#define UC81XX_PTL_FLAG_PT_SCAN BIT(0) |
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/* Time constants in ms */ |
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#define UC81XX_RESET_DELAY 10U |
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#define UC81XX_PON_DELAY 100U |
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#define UC81XX_BUSY_DELAY 1U |
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#endif /* ZEPHYR_DRIVERS_DISPLAY_UC81XX_REGS_H_ */
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