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95 lines
3.3 KiB
95 lines
3.3 KiB
/* |
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* Copyright (c) 2020 Teslabs Engineering S.L. |
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* Copyright (c) 2021 Krivorot Oleg <krivorot.oleg@gmail.com> |
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* Copyright (c) 2022 Konstantinos Papadopoulos <kostas.papadopulos@gmail.com> |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#ifndef ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9342C_H_ |
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#define ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9342C_H_ |
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#include <zephyr/device.h> |
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/* Commands/registers. */ |
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#define ILI9342C_GAMSET 0x26 |
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#define ILI9342C_IFMODE 0xB0 |
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#define ILI9342C_FRMCTR1 0xB1 |
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#define ILI9342C_INVTR 0xB4 |
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#define ILI9342C_DISCTRL 0xB6 |
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#define ILI9342C_ETMOD 0xB7 |
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#define ILI9342C_PWCTRL1 0xC0 |
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#define ILI9342C_PWCTRL2 0xC1 |
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#define ILI9342C_PWCTRL3 0xC2 |
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#define ILI9342C_VMCTRL1 0xC5 |
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#define ILI9342C_SETEXTC 0xC8 |
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#define ILI9342C_PGAMCTRL 0xE0 |
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#define ILI9342C_NGAMCTRL 0xE1 |
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#define ILI9342C_IFCTL 0xF6 |
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/* Commands/registers length. */ |
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#define ILI9342C_GAMSET_LEN 1U |
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#define ILI9342C_IFMODE_LEN 1U |
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#define ILI9342C_FRMCTR1_LEN 2U |
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#define ILI9342C_INVTR_LEN 1U |
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#define ILI9342C_DISCTRL_LEN 4U |
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#define ILI9342C_ETMOD_LEN 1U |
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#define ILI9342C_PWCTRL1_LEN 2U |
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#define ILI9342C_PWCTRL2_LEN 1U |
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#define ILI9342C_PWCTRL3_LEN 1U |
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#define ILI9342C_VMCTRL1_LEN 1U |
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#define ILI9342C_SETEXTC_LEN 3U |
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#define ILI9342C_PGAMCTRL_LEN 15U |
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#define ILI9342C_NGAMCTRL_LEN 15U |
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#define ILI9342C_IFCTL_LEN 3U |
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/** X resolution (pixels). */ |
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#define ILI9342c_X_RES 320U |
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/** Y resolution (pixels). */ |
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#define ILI9342c_Y_RES 240U |
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/** ILI9342C registers to be initialized. */ |
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struct ili9342c_regs { |
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uint8_t gamset[ILI9342C_GAMSET_LEN]; |
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uint8_t ifmode[ILI9342C_IFMODE_LEN]; |
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uint8_t frmctr1[ILI9342C_FRMCTR1_LEN]; |
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uint8_t invtr[ILI9342C_INVTR_LEN]; |
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uint8_t disctrl[ILI9342C_DISCTRL_LEN]; |
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uint8_t etmod[ILI9342C_ETMOD_LEN]; |
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uint8_t pwctrl1[ILI9342C_PWCTRL1_LEN]; |
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uint8_t pwctrl2[ILI9342C_PWCTRL2_LEN]; |
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uint8_t pwctrl3[ILI9342C_PWCTRL3_LEN]; |
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uint8_t vmctrl1[ILI9342C_VMCTRL1_LEN]; |
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uint8_t setextc[ILI9342C_SETEXTC_LEN]; |
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uint8_t pgamctrl[ILI9342C_PGAMCTRL_LEN]; |
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uint8_t ngamctrl[ILI9342C_NGAMCTRL_LEN]; |
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uint8_t ifctl[ILI9342C_IFCTL_LEN]; |
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}; |
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/* Initializer macro for ILI9342C registers. */ |
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#define ILI9342c_REGS_INIT(n) \ |
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static const struct ili9342c_regs ili9342c_regs_##n = { \ |
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.gamset = DT_PROP(DT_INST(n, ilitek_ili9342c), gamset), \ |
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.ifmode = DT_PROP(DT_INST(n, ilitek_ili9342c), ifmode), \ |
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.frmctr1 = DT_PROP(DT_INST(n, ilitek_ili9342c), frmctr1), \ |
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.invtr = DT_PROP(DT_INST(n, ilitek_ili9342c), invtr), \ |
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.disctrl = DT_PROP(DT_INST(n, ilitek_ili9342c), disctrl), \ |
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.etmod = DT_PROP(DT_INST(n, ilitek_ili9342c), etmod), \ |
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.pwctrl1 = DT_PROP(DT_INST(n, ilitek_ili9342c), pwctrl1), \ |
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.pwctrl2 = DT_PROP(DT_INST(n, ilitek_ili9342c), pwctrl2), \ |
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.pwctrl3 = DT_PROP(DT_INST(n, ilitek_ili9342c), pwctrl3), \ |
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.vmctrl1 = DT_PROP(DT_INST(n, ilitek_ili9342c), vmctrl1), \ |
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.setextc = {0xFF, 0x93, 0x42}, \ |
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.pgamctrl = DT_PROP(DT_INST(n, ilitek_ili9342c), pgamctrl), \ |
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.ngamctrl = DT_PROP(DT_INST(n, ilitek_ili9342c), ngamctrl), \ |
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.ifctl = DT_PROP(DT_INST(n, ilitek_ili9342c), ifctl), \ |
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}; |
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/** |
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* @brief Initialize ILI9342C registers with DT values. |
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* |
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* @param dev ILI9342C device instance |
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* @return 0 on success, errno otherwise. |
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*/ |
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int ili9342c_regs_init(const struct device *dev); |
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#endif /* ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9342C_H_ */
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