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284 lines
8.5 KiB
284 lines
8.5 KiB
/* Copyright (c) 2024 Silicon Laboratories Inc. |
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* SPDX-License-Identifier: Apache-2.0 |
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* |
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* Poor man driver for 917 clocks. 917 includes High Performace (HP) clock |
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* (@46000000), Ultra Lower Power (ULP) clock (@24041400) and ULP VBAT (@24048000) |
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* |
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*/ |
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#include <zephyr/dt-bindings/clock/silabs/siwx91x-clock.h> |
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#include <zephyr/drivers/clock_control.h> |
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#include <zephyr/logging/log.h> |
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#include "rsi_power_save.h" |
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#include "rsi_rom_ulpss_clk.h" |
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#include "rsi_rom_clks.h" |
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#include "rsi_sysrtc.h" |
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#include "rsi_pll.h" |
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#include "rsi_adc.h" |
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#include "clock_update.h" |
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#include "sl_si91x_clock_manager.h" |
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#define DT_DRV_COMPAT silabs_siwx91x_clock |
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#define LF_FSM_CLOCK_FREQUENCY 32768 |
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#define XTAL_FREQUENCY 40000000 |
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LOG_MODULE_REGISTER(siwx91x_clock, CONFIG_CLOCK_CONTROL_LOG_LEVEL); |
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struct siwx91x_clock_data { |
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uint32_t enable; |
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}; |
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static int siwx91x_clock_on(const struct device *dev, clock_control_subsys_t sys) |
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{ |
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struct siwx91x_clock_data *data = dev->data; |
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uintptr_t clockid = (uintptr_t)sys; |
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switch (clockid) { |
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case SIWX91X_CLK_ULP_UART: |
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RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_UART); |
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RSI_ULPSS_UlpUartClkConfig(ULPCLK, ENABLE_STATIC_CLK, |
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false, ULP_UART_ULP_MHZ_RC_CLK, 1); |
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break; |
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case SIWX91X_CLK_ULP_I2C: |
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RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_I2C); |
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RSI_ULPSS_PeripheralEnable(ULPCLK, ULP_I2C_CLK, ENABLE_STATIC_CLK); |
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break; |
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case SIWX91X_CLK_ULP_DMA: |
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RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_UDMA); |
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RSI_ULPSS_PeripheralEnable(ULPCLK, ULP_UDMA_CLK, ENABLE_STATIC_CLK); |
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break; |
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case SIWX91X_CLK_UART0: |
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RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); |
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/* RSI_CLK_UsartClkConfig() calls RSI_CLK_PeripheralClkEnable(); */ |
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RSI_CLK_UsartClkConfig(M4CLK, ENABLE_STATIC_CLK, 0, USART1, 0, 1); |
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break; |
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case SIWX91X_CLK_UART1: |
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RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); |
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/* RSI_CLK_UsartClkConfig() calls RSI_CLK_PeripheralClkEnable(); */ |
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RSI_CLK_UsartClkConfig(M4CLK, ENABLE_STATIC_CLK, 0, USART2, 0, 1); |
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break; |
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case SIWX91X_CLK_I2C0: |
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RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); |
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RSI_CLK_I2CClkConfig(M4CLK, true, 0); |
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break; |
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case SIWX91X_CLK_I2C1: |
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RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); |
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RSI_CLK_I2CClkConfig(M4CLK, true, 1); |
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break; |
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case SIWX91X_CLK_DMA0: |
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RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); |
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RSI_CLK_PeripheralClkEnable(M4CLK, UDMA_CLK, ENABLE_STATIC_CLK); |
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break; |
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case SIWX91X_CLK_PWM: |
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RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); |
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RSI_CLK_PeripheralClkEnable(M4CLK, PWM_CLK, ENABLE_STATIC_CLK); |
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break; |
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case SIWX91X_CLK_WATCHDOG: |
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/* Both SYSRTC and WDT are clocked using LF-FSM XTAL which is initialized in |
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* SystemCoreClockUpdate(). This function allows clock to stabilize before use. |
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*/ |
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rsi_sysrtc_clk_set(RSI_SYSRTC_CLK_32kHz_Xtal, 0); |
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break; |
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case SIWX91X_CLK_GSPI: |
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RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); |
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RSI_CLK_GspiClkConfig(M4CLK, GSPI_INTF_PLL_CLK); |
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break; |
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case SIWX91X_CLK_QSPI: |
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RSI_CLK_Qspi2ClkConfig(M4CLK, QSPI_ULPREFCLK, 0, 0, 0); |
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break; |
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case SIWX91X_CLK_RTC: |
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/* Already done in sl_calendar_init()*/ |
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RSI_PS_NpssPeriPowerUp(SLPSS_PWRGATE_ULP_MCURTC | SLPSS_PWRGATE_ULP_TIMEPERIOD); |
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break; |
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case SIWX91X_CLK_I2S0: |
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RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); |
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break; |
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case SIWX91X_CLK_STATIC_I2S0: |
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MISC_CFG_MISC_CTRL1 |= (1 << 23); |
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RSI_CLK_PeripheralClkEnable(M4CLK, I2SM_CLK, ENABLE_STATIC_CLK); |
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break; |
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case SIWX91X_CLK_ULP_I2S: |
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RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_I2S); |
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break; |
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case SIWX91X_CLK_STATIC_ULP_I2S: |
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ULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_MASTER_SLAVE_MODE_b = 1; |
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RSI_ULPSS_PeripheralEnable(ULPCLK, ULP_I2S_CLK, ENABLE_STATIC_CLK); |
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break; |
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case SIWX91X_ADC_CLK: |
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RSI_ADC_PowerControl(ADC_POWER_ON); |
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break; |
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default: |
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return -EINVAL; |
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} |
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data->enable |= BIT(clockid); |
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return 0; |
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} |
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static int siwx91x_clock_off(const struct device *dev, clock_control_subsys_t sys) |
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{ |
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struct siwx91x_clock_data *data = dev->data; |
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uintptr_t clockid = (uintptr_t)sys; |
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switch (clockid) { |
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case SIWX91X_CLK_ULP_I2C: |
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RSI_ULPSS_PeripheralDisable(ULPCLK, ULP_I2C_CLK); |
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break; |
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case SIWX91X_CLK_ULP_DMA: |
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RSI_ULPSS_PeripheralDisable(ULPCLK, ULP_UDMA_CLK); |
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break; |
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case SIWX91X_CLK_UART0: |
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RSI_CLK_PeripheralClkDisable(M4CLK, USART1_CLK); |
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break; |
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case SIWX91X_CLK_UART1: |
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RSI_CLK_PeripheralClkDisable(M4CLK, USART2_CLK); |
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break; |
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case SIWX91X_CLK_DMA0: |
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RSI_CLK_PeripheralClkDisable(M4CLK, UDMA_CLK); |
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break; |
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case SIWX91X_CLK_STATIC_I2S0: |
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RSI_CLK_PeripheralClkDisable(M4CLK, I2SM_CLK); |
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break; |
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case SIWX91X_CLK_STATIC_ULP_I2S: |
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RSI_ULPSS_PeripheralDisable(ULPCLK, ULP_I2S_CLK); |
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break; |
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case SIWX91X_ADC_CLK: |
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RSI_ADC_PowerControl(ADC_POWER_OFF); |
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break; |
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case SIWX91X_CLK_ULP_UART: |
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case SIWX91X_CLK_I2C0: |
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case SIWX91X_CLK_I2C1: |
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/* Not supported */ |
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return 0; |
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default: |
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return -EINVAL; |
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} |
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data->enable &= ~BIT(clockid); |
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return 0; |
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} |
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static int siwx91x_clock_get_rate(const struct device *dev, clock_control_subsys_t sys, |
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uint32_t *rate) |
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{ |
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uintptr_t clockid = (uintptr_t)sys; |
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switch (clockid) { |
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case SIWX91X_CLK_ULP_UART: |
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*rate = RSI_CLK_GetBaseClock(ULPSS_UART); |
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return 0; |
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case SIWX91X_CLK_UART0: |
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*rate = RSI_CLK_GetBaseClock(M4_USART0); |
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return 0; |
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case SIWX91X_CLK_UART1: |
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*rate = RSI_CLK_GetBaseClock(M4_UART1); |
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return 0; |
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case SIWX91X_CLK_PWM: |
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/* PWM peripheral operates at the system clock frequency */ |
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*rate = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC; |
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return 0; |
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case SIWX91X_CLK_WATCHDOG: |
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*rate = LF_FSM_CLOCK_FREQUENCY; |
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return 0; |
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case SIWX91X_CLK_GSPI: |
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*rate = RSI_CLK_GetBaseClock(M4_GSPI); |
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return 0; |
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default: |
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/* For now, no other driver need clock rate */ |
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return -EINVAL; |
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} |
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} |
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static int siwx91x_clock_set_rate(const struct device *dev, clock_control_subsys_t sys, |
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clock_control_subsys_rate_t rate) |
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{ |
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ARG_UNUSED(dev); |
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int div_numerator = FIELD_GET(0xFFFF0000, *(uint32_t *)rate); |
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int div_denominator = FIELD_GET(0x0000FFFF, *(uint32_t *)rate); |
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uintptr_t clockid = (uintptr_t)sys; |
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ULP_I2S_CLK_SELECT_T ref_clk; |
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uint32_t freq; |
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int ret; |
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switch (clockid) { |
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case SIWX91X_CLK_I2S0: |
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RSI_CLK_SetI2sPllFreq(M4CLK, *((uint32_t *)rate), XTAL_FREQUENCY); |
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RSI_CLK_I2sClkConfig(M4CLK, I2S_PLLCLK, 0); |
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return 0; |
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case SIWX91X_CLK_ULP_I2S: |
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ref_clk = ULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b; |
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freq = RSI_CLK_GetBaseClock(ULPSS_I2S); |
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ret = RSI_ULPSS_UlpI2sClkConfig(ULPCLK, ref_clk, freq / (*((uint32_t *)rate) / 2)); |
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if (ret) { |
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return -EIO; |
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} |
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return 0; |
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case SIWX91X_ADC_CLK: |
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RSI_ADC_ClkDivfactor(AUX_ADC_DAC_COMP, div_numerator, div_denominator); |
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return 0; |
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default: |
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/* For now, no other driver need clock rate */ |
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return -EINVAL; |
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} |
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} |
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static enum clock_control_status siwx91x_clock_get_status(const struct device *dev, |
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clock_control_subsys_t sys) |
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{ |
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struct siwx91x_clock_data *data = dev->data; |
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uintptr_t clockid = (uintptr_t)sys; |
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if (data->enable & BIT(clockid)) { |
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return CLOCK_CONTROL_STATUS_ON; |
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} else { |
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return CLOCK_CONTROL_STATUS_OFF; |
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} |
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} |
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static int siwx91x_clock_init(const struct device *dev) |
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{ |
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SystemCoreClockUpdate(); |
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sl_si91x_clock_manager_init(); |
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/* Use SoC PLL at configured frequency as core clock */ |
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sl_si91x_clock_manager_m4_set_core_clk(M4_SOCPLLCLK, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC); |
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/* Use interface PLL at configured frequency as peripheral clock */ |
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sl_si91x_clock_manager_set_pll_freq(INFT_PLL, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, |
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PLL_REF_CLK_VAL_XTAL); |
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/* FIXME: Currently the clock consumer use clocks without power on them. |
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* This should be fixed in drivers. Meanwhile, get the list of required |
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* clocks using DT labels. |
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*/ |
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ulpi2c), okay) |
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siwx91x_clock_on(dev, (clock_control_subsys_t)SIWX91X_CLK_ULP_I2C); |
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#endif |
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c0), okay) |
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siwx91x_clock_on(dev, (clock_control_subsys_t)SIWX91X_CLK_I2C0); |
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#endif |
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c1), okay) |
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siwx91x_clock_on(dev, (clock_control_subsys_t)SIWX91X_CLK_I2C1); |
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#endif |
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return 0; |
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} |
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static DEVICE_API(clock_control, siwx91x_clock_api) = { |
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.on = siwx91x_clock_on, |
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.off = siwx91x_clock_off, |
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.get_rate = siwx91x_clock_get_rate, |
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.set_rate = siwx91x_clock_set_rate, |
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.get_status = siwx91x_clock_get_status, |
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}; |
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#define SIWX91X_CLOCK_INIT(p) \ |
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static struct siwx91x_clock_data siwx91x_clock_data_##p; \ |
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DEVICE_DT_INST_DEFINE(p, siwx91x_clock_init, NULL, &siwx91x_clock_data_##p, NULL, \ |
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PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, \ |
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&siwx91x_clock_api); |
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DT_INST_FOREACH_STATUS_OKAY(SIWX91X_CLOCK_INIT)
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