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36 lines
492 B
36 lines
492 B
/* |
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* Copyright (c) 2025 Intel Corporation |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/dts-v1/; |
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#include <mem.h> |
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#define DT_DRAM_SIZE DT_SIZE_M(2048) |
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#include <intel/bartlett_lake_s.dtsi> |
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/ { |
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model = "intel_btl_s_crb"; |
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compatible = "intel,bartlett-lake-crb"; |
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chosen { |
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zephyr,sram = &dram0; |
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zephyr,console = &uart_ec_0; |
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zephyr,shell-uart = &uart_ec_0; |
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}; |
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aliases { |
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watchdog0 = &tco_wdt; |
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rtc = &rtc; |
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}; |
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}; |
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&uart_ec_0 { |
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status = "okay"; |
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}; |
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&rtc { |
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status = "okay"; |
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};
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