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52 lines
1.8 KiB
52 lines
1.8 KiB
/* |
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* Copyright (c) 2024 DNDG srl |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <zephyr/kernel.h> |
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#include <zephyr/init.h> |
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#include <stm32h7xx_ll_bus.h> |
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#include <stm32h7xx_ll_gpio.h> |
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static int board_gpio_init(void) |
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{ |
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/* The external oscillator that drives the HSE clock should be enabled |
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* by setting the GPIOI1 pin. This function is registered at priority |
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* PRE_KERNEL_1 to be executed before the standard STM clock |
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* setup code. |
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* |
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* Note that the HSE should be turned on by the M7 only because M4 |
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* is not booted by default on Opta and cannot configure the clocks |
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* anyway. |
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*/ |
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#ifdef CONFIG_BOARD_ARDUINO_OPTA_STM32H747XX_M7 |
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LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOH); |
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LL_GPIO_SetPinMode(GPIOH, LL_GPIO_PIN_1, LL_GPIO_MODE_OUTPUT); |
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LL_GPIO_SetPinSpeed(GPIOH, LL_GPIO_PIN_1, LL_GPIO_SPEED_FREQ_LOW); |
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LL_GPIO_SetPinOutputType(GPIOH, LL_GPIO_PIN_1, LL_GPIO_OUTPUT_PUSHPULL); |
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LL_GPIO_SetPinPull(GPIOH, LL_GPIO_PIN_1, LL_GPIO_PULL_UP); |
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LL_GPIO_SetOutputPin(GPIOH, LL_GPIO_PIN_1); |
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#endif |
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/* The ethernet adapter is enabled by settig the GPIOJ15 pin to 1. |
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* This is done only if the network has been explicitly configured |
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*/ |
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#ifdef CONFIG_NET_L2_ETHERNET |
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LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOJ); |
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LL_GPIO_SetPinMode(GPIOJ, LL_GPIO_PIN_15, LL_GPIO_MODE_OUTPUT); |
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LL_GPIO_SetPinSpeed(GPIOJ, LL_GPIO_PIN_15, LL_GPIO_SPEED_FREQ_LOW); |
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LL_GPIO_SetPinOutputType(GPIOJ, LL_GPIO_PIN_15, LL_GPIO_OUTPUT_PUSHPULL); |
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LL_GPIO_SetPinPull(GPIOJ, LL_GPIO_PIN_15, LL_GPIO_PULL_NO); |
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/* No timer active yet, time a >200us pulse with CPU cycles */ |
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LL_GPIO_ResetOutputPin(GPIOJ, LL_GPIO_PIN_15); |
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for (int i = 0; i < 50000; i++) { |
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arch_nop(); |
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} |
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LL_GPIO_SetOutputPin(GPIOJ, LL_GPIO_PIN_15); |
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#endif |
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return 0; |
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} |
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SYS_INIT(board_gpio_init, PRE_KERNEL_1, 0);
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